LPC1768 clock detailed explanation

LPC1768 has three independent clock sources that can be configured through software. After the MCU is powered on and successfully reset, the internal RC oscillator starts to oscillate and uses this as the operating frequency to read the code in the internal ROM area to perform initialization work, including the configuration of the system clock (in the file system_LPC17xx.c).

The process of system clock configuration is as follows:

The LPC1700 series Cortex-M3 microcontroller includes three independent oscillators, namely the main oscillator (usually refers to the external crystal oscillator), the internal RC oscillator and the RTC oscillator. Each oscillator can be selected according to specific application requirements (by configuring the clock source selection register CLKSRCSEL), the register configuration is as follows

                                                                             Table 1 Clock source selection register bit description

NOTE: Note the following restrictions regarding clock source selection:

1. The accuracy of IRC does not meet the time base accuracy requirements of the USB interface, so the IRC oscillator should not be used as the clock source of the USB subsystem (through PLL0) (USB requires a 48MHz clock source with a duty cycle of 50%);

2. If the CAN baud rate is higher than 100kbit/s, the IRC oscillator should not be used as the clock source for the CAN controller (via PLL0)

It is worth mentioning that LPC1768 has a register specifically for the main oscillator called the System Control and Status Register (SCS). Before selecting the main oscillator as the clock source, you need to configure this register. In this register, you can configure the frequency range of the main oscillator, enable the main oscillator, or read the status of the main oscillator (whether it is stable). The bit description is as follows:

       Table 2 System Control and Status Register (SCS) bit description

After the clock source is determined, the PLL will up-convert the input clock source and then divide it down to provide the actual clock used by the CPU, peripherals, or USB subsystem. It should be noted that the USB subsystem has its own specific PLL (see the description of "PLL1"). PLL0 can generate clock frequencies up to 100MHz, which is the maximum allowed by the CPU.

The multiplication and division values ​​are changed by writing to MSEL0 and NSEL0 in the PLL0 configuration register (PLL0CFG). The register bit description is shown in Table 2.

Table 3 PLL0 configuration register bit description

Note: When configuring PLL0, the correct feed sequence must be written to the PLL0FEED register for changes in the PLL0CON and PLL0CFG registers to take effect. See the manual for PLL0 Feed Registers.

Formula for PLL0 output frequency (when PLL0 is activated and connected):

Fcco = (2 × M × FIN) / N.

Fcco represents the frequency value output after being processed by PLL0. If you want to provide operating frequency for the CPU and peripherals, they also need to be divided by clock dividers, such as the CPU clock configuration register (CCLKCFG), USB clock configuration register (USBCLKCFG), etc.

If you want to configure the values ​​of M and N as needed, refer to Section 4.5.11 "Process for Determining PLL0 Frequency Parameters" in the "Timing and Power Control" chapter of the manual.

When building the LPC1768 project, we need to add the "system_17XX.c" file. The main function of this file is to configure the system clock. The configuration process is basically the same as this article.