Clock tree and clock initialization of STM32F10X

For beginners, clock is a very important and profound concept. For the STM32 chip, in order to achieve low power consumption, a functional but complex clock system is designed to make the clock of peripheral functions configurable. Correspondingly, the clocks of the microcontroller are basically fixed and can be used after a simple configuration. The peripheral functions of the STM32 not only need to be configured, but also need to set these peripheral clocks at the very beginning. Only after these peripheral clocks are enabled can these peripherals be used.

The clock tree of STM32 is shown in the figure below:

STM32 has the following 4 clock sources:

(1) High-speed external clock (HSE): An external crystal oscillator is used as the clock source. The crystal oscillator frequency can range from 4 to 16 MHz. We generally use an 8 MHz crystal oscillator. The 8 MHz clock on the development board refers to this.

(2) High-speed internal clock (HSI): Generated by an internal RC oscillator with a frequency of 8MHz, but it is unstable.

(3) Low-speed external clock (LSE): uses an external crystal oscillator as the clock source, mainly provided to the real-time clock module, so 32.768KHz is generally used. The STM32F103CBT6 development board uses a 32.768KHz crystal oscillator.

 (4) Low-speed internal clock (LSI): Generated by the internal RC oscillator and mainly provided to the real-time clock module, with a frequency of approximately 40KHz.

Next, we will take the most commonly used high-speed external clock (HSE) as an example for analysis:

1) Starting from the left end, OSC_OUT and OSC_IN, these two pins are connected to the two ends of the external crystal oscillator.

2) The 8MHz clock encounters the first divider PLLXTPRE (HSE divider for PLL entry). In this divider, you can select its output through register configuration. Its output clock can be a 2-way divider of the input clock or no divider. In this example, we choose no divider, so after passing through PLLXTPRE, it is still an 8MHz clock.

3) The 8MHz clock encounters the switch PLLSRC (PLL entry clock source). We can choose its output, either external high-speed clock (HSE) or internal high-speed clock (HSI). Here we choose to output HSE, and then encounter the phase-locked loop PLL, which has a frequency multiplication function. Here we can enter the frequency multiplication factor PLLMUL (PLL multiplication factor). If you want to overclock, you have to do something with this register. The clock that passes through the PLL is called PLLCLK. We set the frequency multiplication factor to 9 times, that is, after passing through the PLL, our clock changes from the original 8MHz HSE to 72MHz PLLCLK.

4) Then we come across a switch SW, after which comes the system clock (SYSCLK) of STM32. Through this switch, we can switch the clock source of SYSCLK, which can be HSI, PLLCLK, or HSE. We choose PLLCLK clock, so SYSCLK is 72MHz.

5) Before being input to SW, PLLCLK also flows to the USB pre-divider, and the output of this divider is the clock (USBCLK) of the USB peripheral.

6) Back to SYSCLK, SYSCLK passes through the AHB pre-divider, and is input to other peripherals after frequency division. For example, it is output to clocks called HCLK and FCLK, and is also directly output to the SDIOCLK clock of the SDIO peripheral, the FSMCCLK clock of the memory controller FSMC, and the input of the pre-divider of APB1 and APB2. In this example, the AHB pre-divider is set to no frequency division, that is, the output frequency is 72MHz.

From the analysis of the clock tree, we can see that after a series of frequency multiplication and division, we get several clocks that are closely related to our development.

SYSCLK: System clock, the clock source of most STM32 devices. It is mainly distributed to various components by the AHB prescaler.

HCLK: It is directly output by the AHB pre-divider. It is the clock signal of the high-speed bus AHB, which is provided to the memory, DMA and cortex core. It is the clock for the cortex core to run. The CPU main frequency is this signal. Its size is closely related to the STM32 computing speed and data access speed.

FCLK: Also obtained from the output of the AHB prescaler, it is the "free running clock" of the core. "Free" means that it does not come from the clock HCLK, so FCLK continues to run when the HCLK clock stops. Its existence can ensure that when the processor is in sleep mode, it can also sample and interrupt and track sleep events. It is synchronized with HCLK.

PCLK1: Peripheral clock, obtained by the output of the APB1 prescaler, with a maximum frequency of 36MHz, provided to peripherals mounted on the APB1 bus.

PCLK2: Peripheral clock, obtained by the output of the APB2 prescaler, with a maximum frequency of 72MHz, provided to peripherals mounted on the APB2 bus.

Why is the clock system of STM32 so complicated, with frequency multiplication, frequency division and a series of peripheral clock switches. Frequency multiplication is needed to take into account electromagnetic compatibility. For example, if a 72MHz crystal oscillator is directly provided externally, too high an oscillation frequency may bring certain difficulties to the production of circuit boards. Frequency division is because STM32 has both high-speed and low-speed peripherals, and the operating frequencies of various peripherals are not the same, just like the north and south bridges on a PC, which manage high-speed and low-speed devices separately. Finally, each peripheral is equipped with a peripheral clock switch. When we do not use a peripheral, we can turn off the peripheral clock, thereby reducing the overall power consumption of STM32. Therefore, when we use peripherals, we must remember to turn on the peripheral clock first.

For the default startup file "startup_stm32f10x_hd.s" of STM32, for the clock initialization function, tracing to the end, it will jump to the following program:

static void SetSysClock(void)  

{  

#ifdef SYSCLK_FREQ_HSE  

  SetSysClockToHSE();  

#elif defined SYSCLK_FREQ_24MHz  

  SetSysClockTo24();  

#elif defined SYSCLK_FREQ_36MHz  

  SetSysClockTo36();  

#elif defined SYSCLK_FREQ_48MHz  

  SetSysClockTo48();  

#elif defined SYSCLK_FREQ_56MHz  

  SetSysClockTo56();    

#elif defined SYSCLK_FREQ_72MHz  

  SetSysClockTo72();  

#endif  

 /* If none of the define above is enabled, the HSI is used as System clock 

    source (default after reset) */   

}  

Looking at the macro definition, we find that the system clock will be set to 72MHz. This is not difficult to understand. First, the system clock is multiplied to the maximum, and then the peripheral clock can be divided to the required frequency, so that the maximum performance of the CPU can be brought into play.