CortexM3,CortexM4 memory map

Cortex-M3 Memory Map

CM3 has a single fixed memory map. This greatly facilitates the porting of software between various CM3 microcontrollers. For example, the NVIC and MPU of each CM3 microcontroller have registers in the same location, making them universal. However, the rules set by CM3 are broad, and it still allows chip manufacturers to 
flexibly allocate memory space to create unique microcontroller products.

The address space of CM3 is 4GB, and the program can be executed in the code area, internal SRAM area and external RAM area. However, because the instruction bus and data bus are separate, the best way is to put the program in the code area so that instruction fetch and data access can use their own bus and run in parallel.

This is the LPC18xx Memory mapping. 
 
As you can see, the local SRAM is actually in the Code area specified by ARM. It seems that this is not a hard and fast rule, and each chip manufacturer can still adjust it flexibly.

This is STM32F101XC DE Memory mapping 

Comparing with the above figure, we can see that each chip manufacturer defines the memory mapping of its own chip according to ARM's rough memory mapping regulations.

Cortex-M4 memory map (consistent with M3 definition)

Special cases encountered

This is QN908x Memory mapping 

I checked the datasheet and found that the address of SRAM does start from 0x20000000. 

However, the address in the above picture is marked as Aliased to SRAM. The area marked as SRAM starts at 0x040000000. 
I open the .scf file of the sample program again. 

There is confusion here. I will log it after I figure it out.