MSP430+DMA

Hardware Introduction:

The MSP430F15X/16X series microcontrollers have a DMA controller, which can provide a guarantee for high-speed data transmission. For example, the DMA controller can directly transfer the contents of the ADC conversion memory to the RAM unit.

The DMA extended by the MSP430 series microcontroller has triggers from all peripherals, and can provide advanced configurable data transmission capabilities without CPU intervention, thereby accelerating the signal processing process based on the MCU. The trigger source of DMA transmission is completely transparent to the CPU, and the DMA controller can perform precise transmission control between the memory and the external and external hardware. DMA eliminates data transmission delay time and various overheads, thereby freeing up the 16-bit RISC CPU so that it can spend more time processing data rather than executing the tasks being processed.

The DMA module of the MSP430F16x series microcontroller has the following features: Data transfer does not require CPU intervention and is completely managed by the DMA controller. Data can be transferred within the entire address space, and block transfer can reach 65536 bytes; it can improve the data throughput of on-chip peripherals and achieve high-speed transmission. The transmission of each word or byte only requires 2 MCLKs; it reduces system power consumption, and the CPU can be in ultra-low power mode without waking up even when data is input or output by on-chip peripherals; Byte and word data can be mixed: DMA transfer can be byte to byte, word to word, byte to word, or word to byte. When word to byte transfer, only the lower byte in the word can be transferred. When transferring from byte to word, the lower byte of the word is transferred, and the high byte is automatically cleared; four transfer addressing modes: fixed address to fixed address, fixed address to block address, block address to fixed address, and block address to block address; flexible triggering mode: edge or level triggering. Single, block or burst block transfer mode: each time a DMA operation is triggered, different sizes of data can be transferred as needed

The four addressing modes of DMA are shown in the figure below:

DMA controller module: 3 independent transmission channels: channel 0, channel 1 and channel 2. Each channel has a source address register, a destination address register, a transmission data length register and a control register. The trigger request of each channel can be enabled and disabled separately; Configurable channel priority: Priority decision module, the priority of the transmission channel can be adjusted, and the priority decision is made for the channels with trigger requests at the same time to determine which channel has the highest priority. The DMA controller of MSP430 can use fixed priority or circular priority. Program command control module, before each DMA channel starts to transmit, the CPU must program the relevant commands and mode controls to determine the type of DMA channel transmission; Configurable transmission trigger: trigger source selection module, DMAREQ (software trigger), Timer_ACCR2 output, Timer_BCCR2 output, I2C data reception ready, I2C data transmission ready, USART receive and transmit data, DAC12 module DAC12IFG, ADC12 module ADC12IFGx, DMAxIFG, DMAE0 external trigger source. And it also has the ability to expand the trigger source.

DMA has six transfer modes: single word or single byte transfer; block transfer; burst block transfer; repeated single word or single byte transfer; repeated block transfer; repeated burst block transfer. For the first three, DMAEN is automatically reset after the transfer is completed; the DMAEN bit needs to be reset to enable the DMA channel when transferring again. The last three are repeat modes. After one transfer is completed, DMAEN is not reset; when starting again, data transfer can be started again. The six transfer modes are set through the DMADTx register:

DMADTx      Transfer Mode               Description

000         Single transfer             Each transfer requires a trigger. DMAEN is

                                        automatically cleared when DMAxSZ transfers have

                                        been made.

001         Block transfer              A complete block is transferred with one trigger.

                                        DMAEN is automatically cleared at the end of the

                                        block transfer.

010, 011    Burst-block transfer        CPU activity is interleaved with a block transfer.

                                        DMAEN is automatically cleared at the end of the

                                        burst-block transfer.

100         Repeated single transfer    Each transfer requires a trigger. DMAEN remains

                                        enabled.

101         Repeated block transfer     A complete block is transferred with one trigger.

                                        DMAEN remains enabled.

110, 111    Repeated burst-block        CPU activity is interleaved with a block transfer.

            transfer                    DMAEN remains enabled.

Single word or single byte transfer: The DMA channel is defined as a single word or single byte transfer mode. Each word or byte transfer must be triggered by a trigger signal. Setting DMADTx = 0 defines the single word or single byte transfer mode. After the specified transfer is completed, the DMAEN bit is automatically cleared. If another transfer is required, DMAEN must be reset. If DMADTx = 4 is set to repeat the single word or single byte transfer mode, the DMAEN bit remains set, and each trigger is accompanied by a transfer. The DMAxSZ register saves the number of units transferred. If the register is 0, there is no transfer. Before the transfer, the value of the DMAxSZ register is written to a temporary register, and DMAxSZ is decremented after each operation. When DMAxSZ is decremented to zero, its corresponding temporary register will reset the original value to DMAxSZ, and the corresponding DMAIFG flag is set.

Block transfer mode: In block transfer mode, one data block can be transferred per trigger. Set DMADTx=1 for block transfer mode. After each data block is transferred, the DMAEN bit is automatically cleared. Before triggering the transfer of the next data block, the bit must be reset. During the transfer of a data block, other transfer requests will be ignored. Set DMADTx=5 for repeated block transfer mode. After a data block is transferred, the DMAEN bit remains set. After that, a new trigger can cause another data block transfer. The DMAxSZ register saves the number of units contained in the data block. DMASRCINCR and DMADSTINCR reflect the changes in the destination address and source address during the data block transfer process. During block transfer or repeated block transfer, the values ​​of DMAxSA, DMAxDA, and DMAxSZ registers are written to the corresponding temporary registers. The temporary values ​​corresponding to DMAxSA and DMAxDA registers increase or decrease during block transfer, and DMAxSZ counts down during block transfer, always reflecting how many units of the current data block have not been transferred. When DMAxSZ is reduced to 0, its corresponding temporary register will put the original value back into DMAxSZ, and the corresponding DMAIFG is set. During block transfer, the CPU suspends work and does not participate in data transmission. The data block requires 2×MCLK×DMAxSZ clock cycles. When each data block is transferred, the CPU resumes execution according to the state before the suspension.

Burst block transfer mode: This is similar to the block transfer mode, except that for every 4 words or bytes transferred, the DMA releases the internal bus and the CPU runs 2 MCLK cycles; during the transfer process, the CPU has 20% execution time, and the block transfer requires the DMA to complete the transfer before the CPU can run.

DMA trigger source: The trigger source of each channel is controlled by the DMAxTSELx bits. These bits must be set when the DMAEN bit is 0, otherwise unpredictable DMA triggers may occur.

DMAxTSELx   Operation

0000        DMAREQ bit (software trigger)

0001        TACCR2 CCIFG bit

0010        TBCCR2 CCIFG bit

0011        URXIFG0 (UART/SPI mode), USART0 data received (I2C mode)

0100        UTXIFG0 (UART/SPI mode), USART0 transmit ready (I2C mode)

0101        DAC12_0CTL DAC12IFG bit

0110        ADC12 ADC12IFGx bit

0111        TACCR0 CCIFG bit

1000        TBCCR0 CCIFG bit

1001        URXIFG1 bit

1010        UTXIFG1 bit

1011        Multiplier ready

1100        No action

1101        No action

1110        DMA0IFG bit triggers DMA channel 1

            DMA1IFG bit triggers DMA channel 2

            DMA2IFG bit triggers DMA channel 0

1111        External trigger DMAE0

In addition, the interrupt program of the microcontroller does not affect the DMA transmission. During the DMA transmission process, the microcontroller does not respond to all interrupts except the external NMI interrupt (the NMI interrupt must be responded to when the DMA control bit ENNMI is 1, otherwise it will not be processed); the system interrupt handler must wait until the DMA data transmission is completed before running.

DMA interrupt: During data transmission, when the DMAxSZ register value decreases to 0, DMA sets DMAIFG. The DMA interrupt and DAC12 module share the interrupt vector. When using the interrupt, the software needs to determine which interrupt is the specific one. DMAIFG will not be automatically reset after the interrupt response. When using it, the software must clear the DMAIFG bit.

The DMA registers are as follows:

Register                            Short Form      Register Type   Address     Initial State

DMA control 0                       DMACTL0         Read/write      0122h       Reset with POR

DMA control 1                       DMACTL1         Read/write      0124h       Reset with POR

DMA channel 0 control               DMA0CTL         Read/write      01E0h       Reset with POR

DMA channel 0 source address        DMA0SA          Read/write      01E2h       Unchanged

DMA channel 0 destination address   DMA0DA          Read/write      01E4h       Unchanged

DMA channel 0 transfer size         DMA0SZ          Read/write      01E6h       Unchanged

DMA channel 1 control               DMA1CTL         Read/write      01E8h       Reset with POR

DMA channel 1 source address        DMA1SA          Read/write      01EAh       Unchanged

DMA channel 1 destination address   DMA1DA          Read/write      01ECh       Unchanged

DMA channel 1 transfer size         DMA1SZ          Read/write      01EEh       Unchanged

DMA channel 2 control               DMA2CTL         Read/write      01F0h       Reset with POR

DMA channel 2 source address        DMA2SA          Read/write      01F2h       Unchanged

DMA channel 2 destination address   DMA2DA          Read/write      01F4h       Unchanged

DMA channel 2 transfer size         DMA2SZ          Read/write      01F6h       Unchanged

1. For detailed information about each register, refer to the user guide provided by TI.

2. Program implementation:

   The use of DMA mainly involves the initial setting of DMA registers. After the setting is completed, DMA can automatically transmit data when it receives a trigger signal.

   The setup function is as follows:

void DMAInit(char channel,char trigger,char transMode,char srcMode,char dstMode,

             unsigned int src,unsigned int dst,unsigned int size)

{

    unsigned int *DMAxCTL,*DMAxSA,*DMAxDA,*DMAxSZ;

    DMACTL0 = trigger << (channel << 2);

    DMACTL1 = 0x04; //When DMA receives a trigger request, it waits for the current instruction to be executed

    switch (channel) //Select which DMA channel is currently set

    {

        case 0: 

            DMAxCTL = (unsigned int *)&DMA0CTL;

            DMAxSA = (unsigned int *)&DMA0SA;

            DMAxDA = (unsigned int *)&DMA0DA;

            DMAxSZ = (unsigned int *)&DMA0SZ;

            break;                                      //指针 = 0通道控制

        case 1: 

            DMAxCTL = (unsigned int *)&DMA1CTL;

            DMAxSA = (unsigned int *)&DMA1SA;

            DMAxDA = (unsigned int *)&DMA1DA;

            DMAxSZ = (unsigned int *)&DMA1SZ;

            break;                                      //指针 = 1通道控制

        case 2: 

            DMAxCTL = (unsigned int *)&DMA2CTL;

            DMAxSA = (unsigned int *)&DMA2SA;

            DMAxDA = (unsigned int *)&DMA2DA;

            DMAxSZ = (unsigned int *)&DMA2SZ;

            break;                                      //指针 = 2通道控制

    }

    switch (transMode) //Set the transfer mode of the DMA channel

    {

        case 'S': *DMAxCTL = DMADT_0;   break;          //单次传输

        case 's': *DMAxCTL = DMADT_4;   break;          //重复单次传输

        case 'B': *DMAxCTL = DMADT_1;   break;          //块传输

        case 'b': *DMAxCTL = DMADT_5;   break;          //重复块传输

        case 'I': *DMAxCTL = DMADT_2;   break;          //突发块传输 交错

        case 'i': *DMAxCTL = DMADT_6;   break;          //重复突发块传输 交错

    }

    *DMAxCTL |= (srcMode & 0x04) << 2; //Source word or byte

    *DMAxCTL |= (srcMode & 0x03) << 8; //Source address change method

    *DMAxCTL |= (dstMode & 0x04) << 3; //Destination word or byte

    *DMAxCTL |= (dstMode & 0x03) << 10; //Destination address change method

    *DMAxSA = src;

    *DMAxDA = dst;

    *DMAxSZ = size;

    *DMAxCTL |= DMAEN;                                  //DMA使能

}

The function is more complicated. The function content sets each register according to the parameters. DMACTL0 = trigger << (channel << 2); This is the reference source for setting the corresponding channel. If you don’t understand it, you can look at the register content of DMACTL0; the switch (channel) statement sets the register pointed to by the corresponding pointer according to the channel; then set the parameters accordingly.

When set to non-repeating mode, DMAEN needs to be reset. This program implements the function DMAReEnable:

void DMAReEnable(char channel)

{

    switch (channel)        //使能对应通道

    {

        case 0: DMA0CTL |= DMAEN;   break;      //0通道

        case 1: DMA1CTL |= DMAEN;   break;      //1通道

        case 2: DMA2CTL |= DMAEN;   break;      //2通道

    }

}

This function is relatively simple, it just sets the DMAEN bit of the corresponding channel according to the passed parameters.

When set to software trigger, the software needs to start the DMA program as follows:

void DMAStart(char channel)
{
    switch (channel)        //使能对应通道
    {
        case 0: DMA0CTL |= DMAREQ;  break;      //0通道
        case 1: DMA1CTL |= DMAREQ;  break;      //1通道
        case 2: DMA2CTL |= DMAREQ;  break;      //2通道
    }
}

1. This is similar to the previous function: it just sets a control bit. The function is very simple and will not be explained.

   That’s all for the program implementation. For more details, you can download the program library in the attachment. The program comments are very detailed.

2. Example of use:

   When using this program, the steps are the same as the original one: add the DMA.c file to the project, and then include the DMA.h header file in the source file.

   The sample program is as follows:

#include

#include "DMA.h"

unsigned int a[5] = {8693,5689,2356,23565,5656};

unsigned int b[5];

void main( void )

{

    // Stop watchdog timer to prevent time out reset

    WDTCTL = WDTPW + WDTHOLD;

    ClkInit();

    //Block transfer, 5 words (16 bits) a->b

    DMAInit(0,0x00,'B',3,3,(unsigned int)a,(unsigned int)b,5);

    DMAStart(0);

    //If you need to transfer again without changing the settings, just call DMAReEnable to start the transfer again 

    // If it is a repeated block transfer, there is no need to re-enable DMAReEnable and can be started directly

    //This is just a demonstration of how to use it. In actual applications, you should choose the appropriate trigger source based on your needs.

    //

    LPM0;

}

The sample program is very simple to complete, just assigning the value of one array to another array. The array address is the array name, which is forced to be converted to the required type (unsigned 16 bits) and passed to the function initialization settings. For simplicity, it is set to software startup.

The operation effect is as follows:

After single-stepping through the DMA transfer startup, the result comes out, indicating that DMA transfers data very quickly.