System expansion—both RAM and ROM can be expanded simultaneously

In the following system, 8051 expands the off-chip program memory and data memory at the same time. The chip select signals of the two memories are both grounded, that is, they are valid at the same time. In other words, there is no need to select the two memories.

51 Expand RAM and ROM at the same time

Let's analyze this problem. Although there are two memories in the system, the input and input enable signals of the two memories are different. The program memory has no input enable, and its output enable is controlled by the 8051 pin PSEN. Only when the chip select signal and output enable signal of the program memory are valid at the same time, the program memory bus is connected to the CPU bus. Otherwise, all the bus pins of the program memory are in high impedance state, which is equivalent to disconnecting the memory from the CPU bus.

The input enable terminal of the data memory is WR, which is controlled by P3.6 of 8051. The output enable signal is RD, which is controlled by P3.7 of 8051. The condition for the data memory to be connected to 8051 is that the chip select signal is valid and at least one of the input and output enable signals is valid. It can be seen that in this system, the condition for making the two memories valid at the same time is that PSEN is valid and WR is valid or PSEN is valid and RD is valid.

Both of these situations are impossible, because only one of the three signals PSEN, RD, and WR of the CPU can be valid at any time. Therefore, although the chip selects of the two memories in the system are grounded, they will never work at the same time, which means that there will be no confusion in memory access. It is precisely because the input and output enable signals of the 8051 off-chip data memory and program memory are controlled by different pins of the 8051 that the 8051 off-chip program memory space and data memory space are independent, each of which is 64K. In this system, the 8K external data memory uses the 8051's 64K off-chip data storage logical address, and each physical unit has 8 logical addresses. Similarly, the 8K external program memory occupies the 8051's 64K external program memory logical address, and each physical unit also has 8 logical addresses.