The difference between various clocks of STM32

The clock system is the core of the processor, so before learning all the peripherals of STM32, it is necessary to carefully learn the clock system, which will help you to have a deeper understanding of STM32. 
    The following is a STM32 clock block diagram found on the Internet, which is clearer than the one in the "STM32 Chinese Reference Manual": 
    
    
Important clocks: 
  The relationship between PLLCLK, SYSCLK, HCKL, PCLK1, PCLK2 should be clarified; 


      1. HSI: High-speed internal clock signal. The clock (8M frequency) in the STM32 microcontroller has poor accuracy. 
      2. HSE: High-speed external clock signal. High-precision source (1) HSE external crystal/ceramic resonator (crystal oscillator) (2) HSE user external clock          
      3. LSE: Low-speed external crystal 32.768kHz. Mainly provides an accurate clock source. Generally used as an RTC clock  


in STM32. There are five clock sources, HSI, HSE, LSI, LSE, and PLL.  

　　①. HSI is a high-speed internal clock, RC oscillator, with a frequency of 8MHz. 

　　②. HSE is a high-speed external clock, which can be connected to a quartz/ceramic resonator or an external clock source, with a frequency range of 4MHz~16MHz. 

　　③. LSI is a low-speed internal clock, RC oscillator, with a frequency of 40kHz. 

　　④. LSE is a low-speed external clock connected to a quartz crystal with a frequency of 32.768kHz. 

　　⑤. PLL is a phase-locked loop frequency multiplication output, and its clock input source can be selected as HSI/2, HSE or HSE/2. The frequency multiplication can be selected from 2 to 16 times, but its maximum output frequency must not exceed 72MHz. 

　　The 40kHz LSI is used for the independent watchdog IWDG, and it can also be selected as the clock source of the real-time clock RTC. In addition, the clock source of the real-time clock RTC can also be selected as LSE, or 128-division of HSE. The clock source of RTC is selected by RTCSEL[1:0]. 

　　There is a full-speed USB module in STM32, and its serial interface engine requires a clock source with a frequency of 48MHz. This clock source can only be obtained from the PLL output, and can be selected as 1.5 division or 1 division, that is, when the USB module needs to be used, the PLL must be enabled and the clock frequency is configured to 48MHz or 72MHz. 

　　In addition, STM32 can also select a clock signal to output to the MCO pin (PA8), which can be selected as the 2-division of the PLL output, HSI, HSE, or system clock. 

　　The system clock SYSCLK is the clock source for most components in STM32. The system clock can be selected as PLL output, HSI or HSE. The maximum frequency of the system clock is 72MHz. It is divided by the AHB divider and sent to each module for use. The AHB divider can select 1, 2, 4, 8, 16, 64, 128, 256, 512 divisions. The clock output by the AHB divider is sent to 5 major modules: 

　　①, sent to the HCLK clock used by the AHB bus, core, memory and DMA. 

　　②, sent to the system timer clock of Cortex after 8 division. 

　　③, sent directly to the idle running clock FCLK of Cortex. 

　　④, sent to the APB1 divider. The APB1 divider can be divided into 1, 2, 4, 8, or 16 frequency divisions. One of its outputs is used by the APB1 peripheral (PCLK1, maximum frequency 36MHz), and the other is sent to the timer (Timer) 2, 3, or 4 frequency multipliers. The frequency multiplier can be selected as 1 or 2 times, and the clock output is used by timers 2, 3, and 4. 

　　⑤. Sent to the APB2 divider. The APB2 divider can be divided into 1, 2, 4, 8, or 16 frequency divisions. One of its outputs is used by the APB2 peripheral (PCLK2, maximum frequency 72MHz), and the other is sent to the timer (Timer) 1 frequency multiplier. The frequency multiplier can be selected as 1 or 2 times, and the clock output is used by timer 1. In addition, the APB2 divider has one output for the ADC divider, which is sent to the ADC module after division. The ADC divider can be divided into 2, 4, 6, or 8 times. 

　　Among the above clock outputs, many have enable control, such as AHB bus clock, core clock, various APB1 peripherals, APB2 peripherals, etc. When you need to use a module, remember to enable the corresponding clock first. 

　　It should be noted that the timer multiplier, when the APB division is 1, its multiplier value is 1, otherwise its multiplier value is 2. 

　　The devices connected to APB1 (low-speed peripherals) are: power interface, backup interface, CAN, USB, I2C1, I2C2, UART2, UART3, SPI2, window watchdog, Timer2, Timer3, Timer4. Note that although the USB module requires a separate 48MHz clock signal, it should not be the clock for the USB module to work, but only the clock provided to the serial interface engine (SIE). The clock for the USB module to work should be provided by APB1. 

　　The devices connected to APB2 (high-speed peripherals) are: UART1, SPI1, Timer1, ADC1, ADC2, all ordinary IO ports (PA~PE), and second function IO ports. 


Registers involved: 
RCC register structure, RCC_TypeDeff, is defined in the file "stm32f10x_map.h" as follows:  
typedef struct  
{  
vu32 CR; //HSI,HSE,CSS,  PLL, etc. enable
vu32 CFGR; //PLL, etc. clock source selection and frequency division coefficient setting 
vu32 CIR; // Clear/enable clock ready interrupt 
vu32 APB2RSTR; //Peripheral reset register on APB2 line 
vu32 APB1RSTR; //Peripheral reset register on APB1 line 
vu32 AHBENR; //DMA, SDIO, etc. clock enable 
vu32 APB2ENR; //Peripheral clock enable on APB2 line 
vu32 APB1ENR; //Peripheral clock enable on APB1 line 
vu32 BDCR; //Backup domain control register 
vu32 CSR;             
} RCC_TypeDef; 

You can study the clock block diagram and RCC register above to have a general understanding of the STM32 clock system, and then study it together with the system clock configuration function void Stm32_Clock_Init(u8 PLL) in our "STM32 Incomplete Manual". 

[Quote] :

Clock output enable control
    Many of the above clock outputs have enable control, such as AHB bus clock, core clock, various APB1 peripherals, APB2 peripherals, etc.
When a module needs to be used, the corresponding clock must be enabled first. It should be noted that the timer multiplier, when the APB division is 1, its multiplier value is 1, otherwise its multiplier value is 2.
   The devices connected to APB1 (low-speed peripherals) are: power interface, backup interface, CAN, USB, I2C1, I2C2, UART2, UART3, SPI2, window watchdog, Timer2, Timer3, Timer4. Note that although the USB module requires a separate 48MHz clock signal, it should not be the clock for the USB module to work, but only the clock provided to the serial interface engine (SIE). The clock for the USB module to work should be provided by APB1.
   The devices connected to APB2 (high-speed peripherals) are: GPIO_A-E, USART1, ADC1, ADC2, ADC3, TIM1, TIM8, SPI1, AFIO

Using HSE clock, the program sets the clock parameter flow:
1. Reset the RCC register to the default value RCC_DeInit;
2. Turn on the external high-speed clock crystal HSE RCC_HSEConfig(RCC_HSE_ON);
3. Wait for the external high-speed clock crystal to work HSEStartUpStatus = RCC_WaitForHSEStartUp();
4. Set the AHB clock RCC_HCLKConfig;
5. Set the high-speed AHB clock RCC_PCLK2Config;
6. Set the low-speed AHB clock RCC_PCLK1Config;
7. Set the PLL RCC_PLLConfig;
8. Turn on the PLL RCC_PLLCmd(ENABLE);
9. Wait for PLL to work while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
10. Set the system clock RCC_SYSCLKConfig;
11. Determine whether PLL is the system clock while(RCC_GetSYSCLKSource() != 0x08)
12. Open the peripheral clock to be used RCC_APB2PeriphClockCmd()/RCC_APB1PeriphClockCmd()

The following is the configuration function for RCC in the STM32 software firmware library program (using an external 8MHz crystal oscillator)

void RCC_Configuration(void)

{

  RCC_DeInit();

  RCC_HSEConfig(RCC_HSE_ON); //RCC_HSE_ON——HSE crystal oscillator is turned on (ON)

  HSEStartUpStatus = RCC_WaitForHSEStartUp();

  if(HSEStartUpStatus == SUCCESS) //SUCCESS: HSE crystal oscillator is stable and ready

  {   

    RCC_HCLKConfig(RCC_SYSCLK_Div1); //RCC_SYSCLK_Div1——AHB clock = system clock

    RCC_PCLK2Config(RCC_HCLK_Div1); //RCC_HCLK_Div1——APB2 clock = HCLK

    RCC_PCLK1Config(RCC_HCLK_Div2); //RCC_HCLK_Div2——APB1 clock = HCLK / 2

    FLASH_SetLatency(FLASH_Latency_2); //FLASH_Latency_2 2 delay cycle

    FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); // Prefetch buffer enable

    RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);    

   //PLL input clock = HSE clock frequency; RCC_PLLMul_9——PLL input clock x 9

    RCC_PLLCmd(ENABLE);

    while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) ;    

    RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);

   //RCC_SYSCLKSource_PLLCLK——Select PLL as system clock

    while(RCC_GetSYSCLKSource() != 0x08); //0x08: PLL as system clock

  }

  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |

  RCC_APB2Periph_GPIOC , ENABLE);

//RCC_APB2Periph_GPIOA GPIOA clock

//RCC_APB2Periph_GPIOB GPIOB clock

//RCC_APB2Periph_GPIOC GPIOC clock

//RCC_APB2Periph_GPIOD GPIOD clock

}