SYSCLK system clock, maximum 72MHzHCLK: AHB bus clock, obtained by dividing the system clock SYSCLK, usually without frequency division, equal to the system clock through the bus bridge AHB-->APB.
By setting the frequency division, PCLK1 and PCLK2 clocks can be obtained from HCLK, but the maximum PCLK2 clock can reach 72MHz.
PCLK1 corresponds to APB1 peripheral with a maximum frequency of 36MHz.
PCLK2 corresponds to APB2 peripheral with a maximum frequency of 72MHz.
APB2 is responsible for AD, I/O, advanced TIM, and serial port 1.
APB1 is responsible for DA, USB, SPI, I2C, CAN, serial port 2345, and common TIM
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB1Periph_USART2,ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
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