About STM32 GPIO configuration mode

In fact, the manual has very detailed instructions about GPIO mode, which shows how important it is to read the datasheet carefully! !

First of all, the GPIO port of stm32 is divided into input and output, which is different from the bidirectional IO port used by the 51 microcontroller. This requires that we configure the corresponding input and output mode according to whether we are input or output. Input is the input mode, and output is the output mode. The two cannot be mixed.

The following is how the manual describes the GPIO port: 

During and immediately after reset of the general purpose I/O (GPIO)
, the alternate function is not enabled and the I/O port is configured in floating input mode (CNFx[1:0]=01b,
MODEx[1:0]=00b).
After reset, the JTAG pins are placed in input pull-up or pull-down mode:
─ PA15: JTDI placed in pull-up mode
─ PA14: JTCK placed in pull-down mode
─ PA13: JTMS placed in pull-up mode
─ PB4: JNTRST placed in pull-up mode
When configured as an output, the value written to the output data register (GPIOx_ODR) is output to the corresponding I/O pin. The output driver can be used in
push-pull mode or open-drain mode (when outputting 0, only the N-MOS is turned on).
The input data register (GPIOx_IDR) captures the data on the I/O pin at every APB2 clock cycle.
All GPIO pins have an internal weak pull-up and weak pull-down. When configured as input, they can be activated or disconnected.
From the above description, we know that the default floating input mode after the microcontroller is reset, but the JTAG pins will be set to input pull-up or pull-down mode. In output mode, the output of the output register ODR is sent to the corresponding IO port to achieve high and low levels. Input configuration When the I/O port is configured as input: ● The output buffer is disabled ● The Schmitt trigger input is activated ● Depending on the input configuration (pull-up, pull-down or floating), weak pull-up and pull-down resistors are connected ● The data appearing on the I/O pin is sampled into the input data register at each APB2 clock ● Read access to the input data register can obtain the I/O status. See the manual for input configuration. These points are important.

1) When used as input, the output data register is disconnected from the IO port, which means that even if we operate the output data register in the input state, it will not affect the IO port. For example, any operation we use the library function to directly or indirectly change the output data register is invalid. For example, after initializing a certain IO as a pull-up input, we output the IO port to 0. The operation of outputting 0 is completely invalid and does not work! For example, it is ridiculous to use a multimeter to measure the IO port when it is set as an input! !

2) The data of the IO port is sampled into the input data register at each APB2 clock, which means that if the current mode is input mode, then under the 72M system clock, the input data will be updated approximately every 13ns. For example, when we are writing some communication interface timings, we must pay attention to whether the data can be read in 13ns under the read command. Whether the communication method is valid and the data has arrived to ensure that the read value is accurate, and whether a delay is required (for the case where the communication data is updated slowly).
3) Note that we set it to floating, pull-up or pull-down input. These states are certain when no peripherals are connected. For example, when we say that in floating mode, the input value is uncertain and may be 0 or 1. When the input is pulled up, the input data register is 1, and when the input is pulled down, the input data register value is 0. This is based on the premise that no peripherals are connected! When we test the development board, we must first determine whether the pin is affected by peripherals!

4) STM32 has weak pull-up and weak pull-down, that is, the pull-up resistor has a large resistance value. When no peripheral is connected, the input data register is 1, which is conducive to detecting low-level input; similarly, when the pull-down input is not connected to an external device, the input data register is 0, which is conducive to detecting high-level input. For inputs whose external device level can be high or low, we can set them to floating inputs.

5) The input data register is read-only. In hardware simulation, the value is masked to indicate that it cannot be modified, but the value is accurate! It should be noted that it is meaningless to view the input register IDR in hardware simulation input mode, and it is also meaningless to view the output data register ODR in output mode. Output Configuration When the I/O port is configured as output: ● The output buffer is activated ─ Open-drain mode: '0' on the output register activates the N-MOS, while '1' on the output register puts the port in a high-impedance state (PMOS is never activated). ─ Push-pull mode: '0' on the output register activates the N-MOS, while '1' on the output register activates the P-MOS. ● Schmitt trigger input is activated ● Weak pull-up and pull-down resistors are disabled ● Data appearing on the I/O pin is sampled into the input data register at each APB2 clock ● In open-drain mode, a read access to the input data register obtains the I/O status ● In push-pull mode, a read access to the output data register obtains the last written value. See the manual for the paragraph about output configuration. We need to pay attention to the following points:

1) In output mode, the input register and the IO port are not shielded, and in open-drain output mode, we can actually read the state of our input port by reading the input data register (although it is not recommended to mix output mode and input, it is important to note that this property exists)

2) Characteristics of open-drain output If you want to control peripherals, you must connect an external pull-up resistor, because it does not have the ability to output a high level, but can only output a low level. Of course, this mode that requires an external pull-up resistor also enables us to output any "high level" we want, such as 5V connected to an external 5V pull-up; while push-pull output can output high or low levels. (For more information, see below)

Detailed explanation of push-pull and open-drain output of microcontroller I/O port:

Push-pull output: can output high and low levels, connect digital devices; push-pull structure generally refers to two transistors being controlled by two complementary signals, and one transistor is always turned on while the other is turned off.

Open drain output: The output terminal is equivalent to the collector of the transistor. A pull-up resistor is required to obtain a high level state. It is suitable for current-type driving and has a relatively strong ability to absorb current (generally within 20ma).

Let's first talk about the structure of the open collector output. The structure of the open collector output is shown in Figure 1. The collector of the transistor on the right is not connected to anything, so it is called an open collector (the transistor on the left is used for inversion, so that when the input is "0", the output is also "0"). For Figure 1, when the input on the left is "0", the front transistor is cut off (that is, the collector C and the emitter E are equivalent to being disconnected), so the 5V power supply is added to the transistor on the right through the 1K resistor, and the transistor on the right is turned on (that is, it is equivalent to a closed switch); when the input on the left is "1", the front transistor is turned on, and the back transistor is cut off (equivalent to a closed switch).

We simplify Figure 1 to Figure 2. The switch in Figure 2 is controlled by software and is open when "1" and closed when "0". It is obvious that when the switch is closed, the output is directly grounded, so the output level is 0. When the switch is open, the output terminal is suspended, that is, high impedance state. At this time, the level state is unknown. If a resistive load (even a very light load) is connected to the ground, the level of the output terminal will be pulled to a low level by this load, so this circuit cannot output a high level.

Look at Figure 3 again. The 1K resistor in Figure 3 is the pull-up resistor. If the switch is closed, current will flow through the 1K resistor and the switch, but because the switch closes the other three ports with internal pull-ups, when we want to use the input function, we only need to set the output port to 1, which is equivalent to the switch being disconnected, and for the P0 port, it is a high-impedance state.

For open drain (OD) output, it is very similar to open collector output. Just replace the above transistor with a field effect transistor. In this way, the collector becomes the drain, and OC becomes OD. The principle analysis is the same.

Another output structure is push-pull output. The push-pull output structure is to replace the upper pull-up resistor with a switch. When a high level is to be output, the upper switch is turned on and the lower switch is turned off; when a low level is to be output, it is just the opposite. Compared with OC or OD, such a push-pull structure has strong high and low level driving capabilities. If two output ports with different output levels are connected together, a large current will be generated, which may burn out the output port. The OC or OD output mentioned above will not have such a situation because the current provided by the pull-up resistor is relatively small. If the push-pull output is to be set to a high impedance state, the two switches must be disconnected at the same time (or a transmission gate is used on the output port), so that it can be used as an input state. Some IO ports of AVR microcontrollers have this structure.

Open-drain circuit characteristics and applications

When designing circuits, we often encounter the concepts of open drain and open collector.
The "drain" mentioned in the concept of open drain circuit refers to the drain of MOSFET. Similarly, the "collector" in the open collector circuit refers to the collector of the transistor. An open drain circuit refers to a circuit with the drain of MOSFET as the output. The general usage is to add a pull-up resistor to the circuit outside the drain. A complete open drain circuit should consist of an open drain device and an open drain pull-up resistor. As shown in Figure 1:

The circuits that form the open-drain form have the following characteristics:
    1. Utilize the driving capability of the external circuit to reduce the internal drive of the IC (or drive a load higher than the chip power supply voltage). When the internal MOSFET of the IC is turned on, the driving current flows from the external VCC through R pull-up, MOSFET to GND. Only a very low gate drive current is required inside the IC. See Figure 1.

    2. Multiple open-drain output pins can be connected to one line. This forms an "AND logic" relationship. As shown in Figure 1, when any one of PIN_A, PIN_B, and PIN_C becomes low, the logic on the open-drain line becomes 0. This is also the principle of I2C, SMBus and other buses to determine the bus occupancy status. If it is used as an output, a pull-up resistor must be connected. When connected to a capacitive load, the falling delay is the transistor in the chip, which is actively driven and has a faster speed; the rising delay is a passive external resistor with a slower speed. If high speed is required, the resistance should be small and the power consumption will be large. Therefore, the selection of load resistance should take into account both power consumption and speed.
    3. The transmission level can be changed by changing the voltage of the pull-up power supply. As shown in Figure 2, the logic level of the IC is determined by the power supply Vcc1, and the output high level is determined by Vcc2 (the power supply voltage of the pull-up resistor). In this way, we can use low-level logic to control the output high-level logic (so that you can perform arbitrary level conversion). (For example, adding a pull-up resistor can provide TTL/CMOS level output, etc.)

4. If the open drain pin is not connected to an external pull-up resistor, it can only output a low level (therefore, for the P0 port of the classic 51 single-chip microcomputer, an external pull-up resistor must be added if it wants to have input and output functions, otherwise it cannot output high-level logic). Generally speaking, open drain is used to connect devices of different levels and match the levels.
5. The standard open drain pin generally only has the ability to output. Adding other judgment circuits can have the ability of bidirectional input and output.

6. The normal CMOS output stage consists of two tubes, upper and lower. Removing the upper tube will result in OPEN-DRAIN. This output has two main purposes: level conversion and line-and.

7. The wired-and function is mainly used in situations where multiple circuits pull down the same signal. If this circuit does not want to pull down, it will output a high level. Because the tube on the OPEN-DRAIN is removed, the high level is achieved by an external pull-up resistor. (For a normal CMOS output stage, if one output is high and the other is low, it is equivalent to a power short circuit.)

8. OPEN-DRAIN provides a flexible output mode, but it also has its weakness, which is the delay of the rising edge. Because the rising edge charges the load through an external pull-up passive resistor, when the resistor is small, the delay is small, but the power consumption is large; on the contrary, the delay is large and the power consumption is small. Therefore, if there is a requirement for delay, it is recommended to use the falling edge output.

Notes in application: 1. The principles of open drain and open collector are similar. In many applications, we use open collector circuits instead of open drain circuits. For example, an input pin is required to be driven by an open drain circuit. Then our common driving method is to use a triode to form an open collector circuit to drive it, which is convenient and cost-saving. See Figure 4. 

2. The resistance value of the pull-up resistor R pull-up determines the speed of the edge of the logic level conversion. The larger the resistance value, the lower the speed and the lower the power consumption. Vice versa.
     Push-Pull output is generally called push-pull output. It should be more suitable than CMOS output in CMOS circuits because the push-pull output capacity in CMOS cannot be as large as that of bipolar. The output capacity depends on the area of ​​the output electrode N-tube P-tube inside the IC. Compared with the open drain output, the high and low levels of the push-pull are determined by the power supply of the IC, and it cannot simply perform logical operations. Push-pull is the most commonly used output stage design method in CMOS circuits.
    Of course, open drain is not without cost, that is, the output drive capability is very poor. The statement that the output drive capability is very poor is inaccurate. The drive capability depends on the power of the final transistor in the IC. OD only brings a delay to the rising edge, because the rising edge charges the load through an external pull-up passive resistor. When the resistor is selected to be small, the delay is small, but the power consumption is large. On the contrary, the delay is large and the power consumption is small. OPEN DRAIN provides a flexible output mode, but it also comes at a price. If there is a requirement for delay, it is recommended to use the falling edge output.
    The premise of small resistance and small delay is that the principle of resistor selection should be within the allowable range of the power consumption of the final transistor. Experienced designers will not choose a 1 ohm resistor as a pull-up resistor when using logic chips. At the rising edge of the pulse, the power supply charges the load through the pull-up passive resistor. Obviously, the smaller the resistance, the shorter the rise time. At the falling edge of the pulse, in addition to the load discharging through the active transistor, the power supply also forms a path to the ground through the pull-up resistor and the turned-on transistor, which brings about the power consumption and power consumption of the chip. The resistor affects the rising edge but not the falling edge. If you don't care about the rising edge during use, the pull-up resistor can be selected as large as possible to reduce the current in the path to the ground. If the rising edge time is required to be high, the selection of the resistor size should be based on the chip power consumption.