The STM32 timer sometimes interrupts as soon as it is turned on

    When using the update interrupt of the STM32 timer, it is found that in some cases, an interrupt is immediately entered as long as the timer is turned on. To be precise, as long as the update interrupt enable bit is enabled, an update interrupt is immediately responded to [of course, the premise is that the relevant NVIC has also been configured]. In other words, as long as the relevant timer update interrupt is enabled, no matter how long your timing interval is or even whether you start the relevant timer, it will immediately enter a timer update interrupt service routine.

Taking the STM32F051 chip as an example, several combinations of tests in different orders were conducted. According to the test, in some cases, once TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE); is run, [even if the update interrupt is enabled], the update interrupt service routine is immediately entered. Of course, the subsequent interrupts are normal.

To be honest, this problem is easy to ignore and in some cases it is not important, but in some cases it may cause trouble to the application. It seems that it is not obvious to find a very suitable or logical cause and effect about this problem from the ST MCU related technical manual.

After verification and testing, it was found that this problem can be avoided if attention is paid to the order of relevant instruction codes.
    

First clear the update interrupt flag, that is, clear the UIF flag in the TIMx->SR register, and then enable the timer update interrupt. As for the placement of the instructions to start the relevant timers, it is not strict. The following is the operation sequence and results of the relevant actions, which can be referenced and verified. There are 6 ways of writing listed here, 3 of which will immediately enter the interrupt, and the other 3 will not.
    TIM_ClearITPendingBit(TIM1, TIM_IT_Update); //Clear update interrupt request bit

    TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE); //Enable timer 1 update interrupt

TIM_Cmd(TIM1, ENABLE); //Start the timer

         (1) The update interrupt routine will not be entered immediately.

    TIM_ClearITPendingBit(TIM1, TIM_IT_Update); //Clear update interrupt request bit

TIM_Cmd(TIM1, ENABLE); 

    TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE); //Enable timer 1 update interrupt

     (2) The update interrupt routine will not be entered immediately.
 

TIM_Cmd(TIM1, ENABLE);

   TIM_ClearITPendingBit(TIM1, TIM_IT_Update); //Clear update interrupt request bit

  TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE); //Enable timer 1 update interrupt

   (3) The update interrupt procedure will not be entered immediately.

    TIM_Cmd(TIM1, ENABLE);

    TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE); //Enable timer 1 update interrupt

    TIM_ClearITPendingBit(TIM1, TIM_IT_Update); //Clear update interrupt request bit

       (4) Immediately enter the update interrupt program.

 
     TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE); //Enable timer 1 update interrupt

   TIM_ClearITPendingBit(TIM1, TIM_IT_Update); //Clear update interrupt request bit

TIM_Cmd(TIM1, ENABLE);  

  (5) . . . . . . Enter the update interrupt procedure immediately.
 

     TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE); //Enable timer 1 update interrupt

     TIM_Cmd(TIM1, ENABLE); 

     TIM_ClearITPendingBit(TIM1, TIM_IT_Update); //Clear update interrupt request bit

  (6) . . . . . . Enter the update interrupt procedure immediately.
 

 By the way, let me mention the use of the UG bit and URS bit in the timer, which are in the TIMx->EGR and TIMx->CR1 registers respectively. Setting the UG bit to 1 can generate an update event and reinitialize the related counters and registers. If the URS bit is 0, an update interrupt will be generated at the same time. If you do not want to generate an update interrupt when setting the UG bit to 1, you must set the URS bit to 1, otherwise you will immediately enter the update interrupt.