About STM32F4 timer clock frequency problem

From the clock tree we can know

(1) The clock source of advanced timer timer1, timer8 and general timer timer9, timer10, timer11 is APB2 bus.
(2) The clock source of general timer timer2~timer5, general timer timer12~timer14 and basic timer timer6, timer7 is APB1 bus.

From the internal clock tree of STM32F4, we can see that

(1) When the division number of APB1 and APB2 is 1, the clock of TIM1, TIM8~TIM11 is the clock of APB2, and the clock of TIM2~TIM7, TIM12~TIM14 is the clock of APB1;

(2) If the division ratio of APB1 and APB2 is not 1, the clocks of TIM1, TIM8 to TIM11 are twice the clock of APB2, and the clocks of TIM2 to TIM7, TIM12 to TIM14 are twice the clock of APB1.

According to the clock analysis, click to open the link , we can see

Because the APB1 bus clock is initialized to 42M divided by 4 and the APB2 bus clock is initialized to 84M divided by 2 in the SystemInit function, the clocks of TIM1, TIM8~TIM11 are twice the APB2 clock, i.e. 168M, and the clocks of TIM2~TIM7, TIM12~TIM14 are twice the APB1 clock, i.e. 84M.

Knowing the clock source frequency of the timer, it is very convenient to use the timer for delay. We just need to set the appropriate frequency division coefficient. Here is the formula for delay using interrupts: (from the Atomic STM32F4 Development Guide)
                      Tout = ((arr+1)*(psc+1))/Tclk;
In the formula, psc is the frequency division coefficient, arr is the count value, and when this count is reached, an overflow interrupt will occur. Tclk is the clock source frequency I analyzed above.