STM32 learning notes: CAN bus filter

The STM32 CAN controller provides 28 configurable filter groups (F1 only has 28 for interconnected type, and only 14 for others). 
Each filter group of the STM32 CAN controller consists of two 32-bit registers (CAN_FxR1 and CAN_FxR2, x=0~27). Depending on the bit width, each filter group can provide: 
● 1 32-bit filter, including: STDID[10:0], EXTID[17:0], IDE and RTR bits 
● 2 16-bit filters, including: STDID[10:0], IDE, RTR and EXTID[17:15] bits 
For the filter group, it can be configured as a mask bit mode, so that CAN_FxR0 stores the identifier match value, and 
CAN_FxR1 stores the mask code, that is, if a bit in CAN_FxR1 is 1, the corresponding 
bit in CAN_FxR0 must match the corresponding bit in the identifier of the received frame to pass the filter; the bit in CAN_FxR1 that is 0 
indicates that  the corresponding bit in CAN_FxR0 does not have to match the received frame. The filter group can also be configured as an identifier
list mode, in which case both CAN_FxR0 and CAN_FxR1 contain the identifiers to be matched, and the identifier of the received frame 
must  match one of them to pass the filter.
 
Note: CAN_FilterIdHigh refers to the high 16 bits, and CAN_FilterIdLow refers to the low 16 bits. The frames to be obtained should 
be aligned to the left with the filter setting values. 
Generally, we use ordinary types, so in this article, we can say that STM32 has 14 filter groups. 
According to the configuration, each filter group can have 1, 2 or 4 filters. 
These filters are equivalent to checkpoints. Whenever a message is received, CAN must first " 
pass" the received message through these filters. The messages that can pass are valid messages and are collected into FIFO. The invalid messages that cannot pass are not sent to "me" 
and are directly discarded. 
All filters are connected in parallel, that is, as long as a message passes a filter, it is considered valid. 
Each filter group has two working modes: identifier list mode and identifier mask bit mode. 
In identifier list mode, the identifier of the received message must be exactly equal to the filter value to pass. 
In identifier mask bit mode, you can specify which bits of the identifier are considered to pass when they have what value. This actually limits 
the identifiers in a certain range to pass. 
In a group of filters, the entire group of filters uses the same operating mode. 
In addition, the filter width in each group of filters is variable and can be 32 bits or 16 bits. 
According to the operating mode and width, a filter group can become one of the following forms: 
(1) 1 32-bit mask bit mode filter. 
(2) 2 32-bit list mode filters. 
(3) 2 16-bit mask bit mode filters. 
(4) 4 16-bit list mode filters. 
All filters are connected in parallel, that is, a message is considered valid as long as it passes through one filter. 
Each filter group has two 32-bit registers for storing the "standard values" for filtering, namely FxR1 and FxR2. 
In 32-bit mask bit mode: 
there is 1 filter. 
FxR2 is used to specify which bits need to be concerned, and FxR1 is used to specify the standard values ​​of these bits. 
In 32-bit list mode: 
there are two filters. 
FxR1 specifies the standard value of filter 0. The received message is considered to have passed only if the identifier is exactly the same as FxR1. 
FxR2 specifies the standard value of filter 1. 
In 16-bit mask bit mode: 
there are 2 filters. 
FxR1 configures filter 0, where bits [31-16] specify the bits to be concerned about, and bits [15-0] specify the standard values ​​of these bits. 
FxR2 configures filter 1, where bits [31-16] specify the bits to be concerned about, and bits [15-0] specify the standard values ​​of these bits. 
In 16-bit list mode: 
there are 4 filters. 
Bits [15-0] of FxR1 configure filter 0, and bits [31-16] of FxR1 configure filter 1. 
Bits [15-0] of FxR2 configure filter 2, and bits [31-16] of FxR2 configure filter 3. 
The STM32 CAN has two FIFOs, FIFO0 and FIFO1. For easy distinction, FIFO0 is written as 
FIFO_0 and FIFO1 is written as FIFO_1. 
Each filter group must be associated with and can only be associated with one FIFO. Reset defaults to FIFO_0. 
The so-called "association" means that if the received message passes through a filter, the message will be stored in 
the FIFO connected to the filter. 
On the other hand, each FIFO is associated with a series of filter groups, and the two FIFOs just divide all 
the filter  groups.
Whenever a message is received, CAN compares the message with the filter associated with FIFO_0. If it matches, 
the message is placed in FIFO_0. 
If it does not match, the message is compared with the filter associated with FIFO_1. If it matches, the message is placed 
in FIFO_1. 
If it still does not match, the message is discarded. 
All filters of each FIFO are connected in parallel. As long as any one of the filters is passed, the message is valid. 
If a message meets the requirements of both FIFO_0 and FIFO_1, it will obviously be placed in FIFO_0 according to the order of operations 
. 
Only activated filters in each FIFO work. In other words, if a FIFO has 20 filters 
but only 5 are activated, then when comparing messages, only these 5 filters are compared. 
Generally, when a filter is to be used, it is directly activated during the initialization phase. 
It should be noted that each FIFO must have at least one filter activated before it can receive messages. If no 
filter  is activated, all messages are discarded.
Generally, if you do not want to use complex filtering functions, the FIFO can only activate one set of filters and set it to a 32 
-bit mask bit mode, and both standard value registers (FxR1, FxR2) are set to 0. In this way, all messages can pass. 
(This is what is done in the routine provided by STM32!) 
Another difficult thing to understand in STM32 CAN is the filter number. 
The filter number is used to speed up the CPU's processing of received messages. 
When a valid message is received, CAN will store the received message and the filter number it passed into the 
receiving  mailbox. When the CPU processes it, it can quickly know the purpose of the message based on the filter number, and then make
corresponding processing. 
It is actually possible not to use the filter number. At this time, the CPU must analyze the identifier of the received message to know 
the purpose of the message. 
Because the identifier contains more information, it is slower to process. 
The STM32 uses the following rules to number filters: 
(1) Filters in FIFO_0 and FIFO_1 are numbered independently, starting from 0 and numbered in sequence. 
(2) All filters associated with the same FIFO are numbered uniformly, regardless of whether they are activated or not. 
(3) Numbering starts from 0 and is arranged in order from small to large according to the filter group number. 
(4) Within the same filter group, numbering is done from small to large according to the register. Filters configured with FxR1 have small numbers, and 
filters configured with FxR2 have large numbers. 
(5) Within the same register, numbering is done from small to large according to the bit order. Filters configured with bits [15-0] have small numbers, and 
filters configured with bits [31-16] have large numbers. 
(6) Filter numbering is flexible. When the settings are changed, the number of each filter will change. 
However, if the settings remain unchanged, the numbering of each filter is relatively stable. 
In this way, each filter has its own number in the FIFO. 
In FIFO_0, the numbering is from 0 – (M-1), where M is the total number of its filters. 
In FIFO_1, the numbers are from 0 – (N-1), where N is the total number of its filters. 
If a FIFO has many filters, there may be a message that can pass through several filters. At this 
time  , where does this message come from?
When using filters, STM32 filters in the following order: 
(1) Filters with a bit width of 32 bits have a higher priority than filters with a bit width of 16 bits. 
(2) For filters with the same bit width, the identifier list mode has a higher priority than the mask bit mode. 
(3) For filters with the same bit width and mode, the priority is determined by the filter number, and the smaller the filter number, the higher the priority. 
In this order, the first filter that the message can pass is the filter number of the message and is stored in the receiving mailbox 
.