ARM's convention

byte 8bits 
halfword 16bits 
word 32bits

Instruction set provided by ARM Core

ARM instruction set 32 ​​bits 
Thumb instruction set 16 bits 
Thumb2 instruction set 16&32 bits

Seven working modes of ARM CPU

Except for User mode, which is normal mode, the other 6 modes are Privilege mode. Among the privileged modes, except Sys mode, the other 5 modes are exception modes. 
The switching between the modes can be done manually by the programmer through code (writing CPSR register), or the CPU can automatically switch under certain circumstances. 
The CPU registers that can be accessed in different modes are different.

ARM CPU's 37 registers

 
The CPU registers that can be accessed in different modes are different. The black part in the figure above is the register that can be accessed in user mode. The black part in FIQ is the same as in User mode, and r0 accessed in FIQ mode is the same register as r0 in User mode, while the gray r8 is the register unique to FIQ mode. Similarly, r13 and r14 under IRQ are also private registers in their own mode and can only be accessed in their own mode.

ARM has 37 registers, all of which are 32 bits long. 
Of the 37 registers, 30 are general-purpose, 1 is fixed as PC, 1 is fixed as CPSR, and 5 are fixed as SPSR in 5 exception modes.

The CPSR register is used to indicate certain status information of the CPU. The meaning of each bit is as shown in the figure below. 

The SPSR register is used to save the data in the CPSR when entering the exception mode, and to restore the data in the CPSR when returning to the user mode from the exception mode. 
The r15 register is also called the pc (program control) register, which is the program pointer. Wherever the pc points to, the CPU will execute the instruction pointed to by the address.

ARM exception handling

All processes outside of normal operation are called exceptions. Interrupts are also a type of exception. 
When an exception occurs, the CPU will automatically jump to a fixed address to run. This fixed address is the terminal vector table. The interrupt vector table stores the program addresses to which all exceptions should jump. The exception vector table is the support provided by hardware to software for handling exceptions.

ARM exception handling process: When an exception occurs, first copy CPSR to SPSR_, 
then set the appropriate CPSR bit, change the processor working mode, enter ARM state, perform exception handling, save the return address LR_ and set PC to the corresponding exception vector. 
When the exception returns, restore CPSR from SPSR_ and PC from LR_  .
These operations can only be performed in ARM state.