How to write the test bench file for the verliog10 divider

Gerryi

How to write the test bench file for the verliog10 divider [Copy link]

 

郝旭帅

Actually, what you wrote is correct, but simulation requires initial values. In your design, clkout and cnt have no initial values, so simulation may show red lines. You need to give initial values. For initial values, you can write reg [3:0] cnt = 4'd0; clkout in the same way. With initial values, simulation can be normal.

Gerryi

Gerryi

I don't know where to add the register and CLKOUT

I tried many places, but nothing worked.

okhxyyo

There is a syntax error in the error. First, check whether the code semicolon, left and right brackets are missing. I looked at your code and it should be written as a comma instead of a semicolon.

okhxyyo

Wrong picture.

okhxyyo

When checking for semicolon errors, sometimes the actual error is not on the line where the error message appears. You need to trace it back. The first way is to check if the current line is correct? Are the semicolons in the previous lines correct? Then, are the lines of code that correspond to the variables in this line correct? Are the semicolons correct? Generally, you will not miss it if you follow this line of thinking.

Gerryi

okhxyyo posted on 2020-4-14 07:49 Wrong picture,

The comma here is after the test bench file is generated. My first test bench file runs successfully on modelsim, so it should not be a comma problem. But since I just started learning, I don't know how to express the change of CLKOUT with CLKIN in code.

Gerryi

okhxyyo posted on 2020-4-14 07:54 When checking for semicolon errors, sometimes the actual error is not on the error line. You need to trace it back. The first type is, is this line correct? The semicolons in the previous few lines of code are correct...

Well, thank you very much. I will use this method to check grammatical errors next time.

okhxyyo

Gerryi posted on 2020-4-14 10:44 Well, thank you very much. I will use this method to check grammatical errors in the future.

Look at the reply from Sofa, you did not give the initial value, which is equivalent to your clkin having nothing coming in. Generally, we need to give the clkin waveform when simulating.

Gerryi

okhxyyo posted on 2020-4-14 11:28 Look at the reply from sofa, you did not give the initial value, which is equivalent to your clkin having nothing coming in. Generally, when we simulate, we need to give the clkin wave...

emmm

My test bench gave me the initial value of CKLIN, and then it flipped every 10ns. When I used modelsim to simulate, CLKIN had a waveform

But CLINOUT is always a red line. Then I read the reply and changed it myself, but it was always wrong. I didn’t know where to add CNT and CLKOUT.

chenzhufly

Did you generate this divider using IPcore, or did you write it yourself?

Gerryi

chenzhufly posted on 2020-4-14 16:04 Did you generate the divider through IPcore or write it yourself?

This is from the teacher's class courseware. I wrote a 10-divider based on the code of the 1000-divider.

is similar to this

chenzhufly

Initialize reg[8:0] CNT=9'b0; in this file and see the result