LPC1768 USB usage--macro definition

#ifndef __USBREG_H

#define __USBREG_H

/* usb device interrupt definition usb_devintst usb_devinten usb_devintclr usb_devintdet*/

#define FRAME_INT 0x00000001 //Generate a frame interrupt every 1MS. This interrupt is used in the transmission of synchronous packets.

#define EP_FAST_INT 0x00000002 //Endpoint fast interrupt, set the endpoint priority level in the endpoint interrupt priority

#define EP_SLOW_INT 0x00000004 //Endpoint slow interrupt, set the endpoint priority level in the endpoint interrupt priority

#define DEV_STAT_INT 0x00000008 //Triggered when USB interrupt reset suspend or connection change

#define CCEMTY_INT 0x00000010 //Interrupt when the command code register is empty, indicating that the written command has been executed

#define CDFULL_INT 0x00000020 //The command data register is full, data can now be read

#define RxENDPKT_INT 0x00000040 //The current data packet in the endpoint buffer has been sent to the CPU

#define TxENDPKT_INT 0x00000080 //The packet length passed to the endpoint buffer is equal to the specified maximum length.

#define EP_RLZED_INT 0x00000100 //The endpoint is used. When setting the selected endpoint or the maximum length of the device, complete the setting. Set

#define ERR_INT 0x00000200 //Any bus error interrupt of USB

/* USB data transfer length related*/

#define PKT_LNGTH_MASK 0x000003FF //Mask for setting the length of received and sent packets usb_rxplen usb_txplen

#define PKT_DV 0x00000400 //USB receive packet data is valid in the transmission process, especially in the synchronous endpoint usb_rxplen

#define PKT_RDY 0x00000800 //The length of the USB receive packet indication is valid and can be read at any time (when using PKT_DV) usb_rxplen

/* usb control byte definition usb_ctrl */

#define CTRL_RD_EN 0x00000001 //USB read mode control needs to read data from USB

#define CTRL_WR_EN 0x00000002 //USB write mode control, need to write data to the USB endpoint, automatically cleared when reading and writing are completed

#define CTRL_LOG_ENDPOINT_MASK (0X0F<<2)//2-5 digits

/* USB command register command usb_cmd_code 8-15 bits 02 for read 01 for write 05 for pure command*/

#define CMD_SET_ADDR 0x00D00500 //Set the device address followed by the device address 0-6 for address 7 for device enable 1 device enable 0 The device does not respond to the packet with its own address

#define CMD_CFG_DEV 0x00D80500 //Configure the device to respond to all enabled non-control endpoints (very important)

#define CMD_SET_MODE 0x00F30500 //Set the mode including clock input endpoint output endpoint batch endpoint ack

#define CMD_RD_FRAME 0x00F50500 //frame number

#define DAT_RD_FRAME 0x00F50200 //Read frame number

#define CMD_RD_TEST 0x00FD0500 //Test register

#define DAT_RD_TEST 0x00FD0200 //Read the test register. If usb_clk is running, it will return 0xa50f

#define CMD_SET_DEV_STAT 0x00FE0500 //Set device status including USB connection UAB suspend or USB bus reset

#define CMD_GET_DEV_STAT 0x00FE0500 //Get device status

#define DAT_GET_DEV_STAT 0x00FE0200 //Read device status

#define CMD_GET_ERR_CODE 0x00FF0500 //Get error code

#define DAT_GET_ERR_CODE 0x00FF0200 //Read the error code data. The lower four bits are the error code. 0x0000: no error

#define CMD_RD_ERR_STAT 0x00FB0500 //Read error status including CRC error, PID error, fill error, etc. USB bus errors

#define DAT_RD_ERR_STAT 0x00FB0200 //Read error status

#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) //Write data to the USB command data register, because only bits 16-23 are valid

#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) //USB select endpoint

#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) //Select the endpoint to get the endpoint status, endpoint empty, full or other

#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) //USB select endpoint/clear interrupt

#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) //USB endpoint settings (endpoint enable, endpoint pause rate feedback, etc.)

#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) //

#define CMD_CLR_BUF 0x00F20500

#define DAT_CLR_BUF 0x00F20200 //USB clear endpoint buffer

#define CMD_VALID_BUF 0x00FA0500 //Confirm the buffer. When this command is sent, it tells the endpoint to send the endpoint buffer data to the host when the next in packet comes.

/* Device address setting 0-6 is address 7 is device enable 1 device enable 0 device does not respond to packets with its own address*/

#define DEV_ADDR_MASK 0x7F

#define DEV_EN 0x80

/* Device configuration All enabled non-control endpoints respond */

#define CONF_DVICE 0x01

/* Data definition of setting mode command*/

#define AP_CLK 0x01 //Whether the 48M clock can be turned off in the suspended state

#define INAK_CI 0x02 //Control the nak interrupt of IN endpoint 0 Return nak interrupt only after data processing is successfully completed 1

#define INAK_CO 0x04 //control the nak interrupt of the out endpoint

#define INAK_II 0x08 //interrupt nak interrupt of in endpoint

#define INAK_IO 0x10 //interrupt out endpoint nak interrupt

#define INAK_BI 0x20 // nak interrupt for batch in nak endpoint

#define INAK_BO 0x40 // nak interrupt for bulk out endpoint

/* Command data definition for setting device status*/

#define DEV_CON 0x01 // 0 connect key low level 1 connect pin high level

#define DEV_CON_CH 0x02 //The connection has changed

#define DEV_SUS 0x04 //Device is suspended

#define DEV_SUS_CH 0x08 //Device suspend bit changes

#define DEV_RST 0x10 //Device receives bus reset

/* Error code data definition*/

#define ERR_EC_MASK 0x0F //Error code mask

#define ERR_EA 0x10 // There is an error code

/* Specific definition of error status */

#define ERR_PID 0x01 //PID encoding error

#define ERR_UEPKT 0x02 //Unexpected data packet

#define ERR_DCRC 0x04 //Data crc error

#define ERR_TIMOUT 0x08 //Timeout error

#define ERR_EOP 0x10 //Data packet end error

#define ERR_B_OVRN 0x20 //Buffer overflow

#define ERR_BTSTF 0x40 //bit stuffing error

#define ERR_TGL 0x80 //Error flip bit in data PID

/* Endpoint information returned by the endpoint selection register*/

#define EP_SEL_F 0x01 //in endpoint empty or out endpoint full

#define EP_SEL_ST 0x02 //Pause endpoint indicator

#define EP_SEL_STP 0x04 //The last time the selected endpoint received a setup packet

#define EP_SEL_PO 0x08 //The previously received package is overwritten by the setup package

#define EP_SEL_EPN 0x10 //Device sends nack

#define EP_SEL_B_1_FULL 0x20 //Buffer 1 status 1 full 0 empty

#define EP_SEL_B_2_FULL 0x40 //Buffer 2 status

/* Endpoint status bit setting */

#define EP_STAT_ST 0x01 //Set endpoint to pause (endpoint automatically pauses after receiving setup packet)

#define EP_STAT_DA 0x20 //Set endpoint enable

#define EP_STAT_RF_MO 0x40 //Whether the interrupt endpoint is in rate feedback mode

#define EP_STAT_CND_ST 0x80 //Endpoint condition pause bit

/* Status that can be read when clearing the endpoint*/

#define CLR_BUF_PO 0x01 //The previously received data packet is overwritten by the setup packet

/* DMA interrupt bit definition */

#define EOT_INT 0x01 //dma transmission end interrupt bit

#define NDD_REQ_INT 0x02 //dma DD request interrupt bit

#define SYS_ERR_INT 0x04 //dma system error interrupt bit

#endif