When debugging the carrier communication system, I encountered such a problem: two devices, A and B, both used timers 2~4 for communication, PCLK1 of device A was configured as HCLK, and PCLK1 of device B was configured as 1/2HCLK. During the communication process, it was found that A and B could communicate occasionally and could not communicate occasionally, showing that the communication was not stable. In theory, it should be completely impossible to communicate. After in-depth research on the data sheet of STM32F101C8T6, I found the problem. The screenshot is as follows:
Figure 1 STM32 functional block diagram
Figure 2 STM32 clock system
Keywords：STM32
Reference address：STM32 APB1 bus clock configuration problem
Figure 2 STM32 clock system
From Figure 1, we can see that the APB1 bus is connected to devices such as TIM2~4, UART2~2...WWD, etc. Then from Figure 2, we can see that only the peripherals directly use the APB1 clock as the actual clock, and TIM2~4 are adjusted according to the APB1 clock. Therefore, when the PCLK1 of device B is configured to 1/2HCLK, APB1 is actually configured to 1/2HCLK. At this time, because the frequency division coefficient of APB1 is not 1, the clock used by TIM2~4 is automatically doubled, and the actual frequency is HCLK. Since the frequency division by 2 and then doubled is theoretically consistent with HCLK, factors such as circuit structure will cause the result to be inconsistent with the direct assignment of HCLK, resulting in unstable communication. Finally, by adjusting the PCLK1 of device A to 1/2HCLK, stable communication can be achieved.
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