Choose ARM processor ARM7 or Cortex-M3

Each ARM processor has a specific instruction set architecture (ISA), and a version of the ISA can be implemented by multiple processors. The ISA has evolved with the needs of the embedded market and has multiple versions to date. ARM plans this evolution so that code written on earlier architecture versions can also be executed on subsequent versions (i.e. code compatibility).

1.1.1 Naming convention
Early ARM used the naming convention shown in Figure 1.1 to describe a processor. The letters and numbers after "ARM" indicate the functional features of a processor. As more features are added, the combination of letters and numbers may change. Note: The naming convention does not include the version information of the architecture (ISA).

ARM {x}{y}{z}{T}{D}{M}{I}{E}{J}{F}{-S}
x——series
y——memory management/protection unit
z——cache
T——Thumb 16-bit decoder
D——JTAG debugger
M——fast multiplier
I——embedded trace macro unit
E——enhanced instructions (based on TDMI)
J——Jazelle
F——vector floating point unit
S——synthesizable version
Figure 1.1 Early ARM naming convention

A few additional points about the ARM nomenclature:
? All ARM cores after the ARM7TDMI include the TDMI feature, even if those characters are not included after the "ARM" logo.
? A processor family is a group of processor implementations that share the same hardware features. For example, the ARM7TDMI, ARM740T and ARM720T all share the same family features and are part of the ARM7 family. ? JTAG is described by the
IEEE1149.1 Standard Test Access Port  and Boundary Scan architecture. It is a family of protocols used by ARM to send and receive debug information between processor cores and test equipment. ? The EmbeddedICE macrocell is debug hardware built into the processor for setting breakpoints and watchpoints. ? Synthesizable - means that the processor core is provided in source code form that can be compiled into a form that is easy for EDA tools to use.

With the explosive influx of ARM architecture products into the market in recent years and the high-level requirements for maintaining architectural consistency, ARM reorganized the ARM architecture specifications and defined the Cortex series based on the ARM v7 architecture.

1.1.2 ARM Processor Series
ARM has designed many processors that can be divided into series based on the different cores used. The series division is based on the ARM7, ARM9, ARM10, ARM11 and Cortex cores. The suffix numbers 7, 9, 10 and 11 indicate different core designs. The ascending order of the numbers indicates the increase in performance and complexity. ARM8 was developed and quickly replaced.
Within each series, there are also multiple variations in memory management, cache and TCM processor extensions. ARM continues to make further developments in both the available product series and the different variants within each series.
Table 1.1 summarizes the different functional characteristics of various processors. It is worth noting that the instruction set architecture ( 
ISA) is an important factor in reflecting the performance characteristics of the CPU core. For example, the ARM926EJ-S using the v5TEJ architecture has much higher processing power than the ARM920T processor using the v4T architecture 
at the same operating frequency.

Table 1.1 Different functional features of ARM processors

a: E extension provides enhanced multiplication instructions and saturation operation instructions (DSP)

1.1.2.1 ARM7 Series
The ARM7 core is a von Neumann architecture, with data and instructions using the same bus. The core has a 3-stage pipeline and executes the ARMv4 instruction set.
The ARM7TDMI is the first processor core in a new series launched by ARM in 1995. It is currently a very popular core and has been used in many 32-bit embedded processors. It provides a very good performance-power ratio. The ARM7TDMI processor core has been licensed to many of the world's top semiconductor companies. It is the first core to include the Thumb instruction set, fast multiplication instructions, and embedded ICE debugging technology.
An important change in the ARM7 series is the ARM7TDMI-S. The ARM7TDMI-S has the same operating characteristics as the standard ARM7TDMI, but it is synthesizable (see Section 2.6.1).
The ARM720T is the most flexible member of the ARM7 series because it includes an MMU. The presence of the MMU means that the ARM720T can handle Linux and Microsoft embedded operating systems (such as WinCE). This processor also includes an 8KB unified cache (instruction/data mixed cache). The vector table can be relocated to a higher address by setting a coprocessor 15 (CP15) register.
Another member is the ARM7EJ-S processor, which is also synthesizable. The ARM7EJ-S is very different from other ARM7 processors because it has a 5-stage pipeline and implements the ARMv5TEJ instruction. This version is the only one of the ARM7 processors that provides java acceleration and enhancement instructions without any memory protection.

1.1.2.2 ARM9 Series
The ARM9 series was introduced in 1997. Due to the use of a 5-stage instruction pipeline, the ARM9 processor can run at a higher clock frequency than the ARM7, improving the overall performance of the processor. The memory system was redesigned according to the Harvard architecture, distinguishing between the data D and instruction I buses.
The first processor in the ARM9 series was the ARM920T, which included independent D+I 
caches and an MMU. This processor can be used on operating systems that require virtual memory support. The ARM922T is a variant of the ARM920T with only half the size of the D+I cache.
The ARM940T includes a smaller D+I cache and an MPU. It is designed for applications that do not require running a platform operating system. Both the ARM920T and ARM940T execute v4T architecture instructions.
The next processor in the ARM9 series is based on the ARM9E-S 
core. This core is a synthesizable version of the ARM9 core with the E extension. It has two variants: the ARM946E-S and the ARM966E-S. Both implement v5TE architecture instructions. They also support the optional Embedded Trace Macrocell (ETM), which allows developers to trace the execution of instructions and data on the processor in real time. This is very important when debugging time-critical program sections. The
ARM946E-S includes TCM, cache, and an MPU. The size of the TCM and cache is configurable. The processor is designed for embedded control applications that require deterministic real-time response. The ARM966E has a configurable TCM, but no MPU and cache extensions. The
latest core in the ARM9 product line is the ARM926EJ-S synthesizable processor core, released in 2000. It is designed for small portable Java devices such as 3G mobile phones and personal digital assistants (PDAs). The ARM926EJ-S is the first ARM processor core to include Jazelle technology, which accelerates the execution of Java bytecodes. It also has an MMU, configurable TCM, and D+I 
cache with zero or non-zero wait memory.

1.1.2.3 ARM10 Series
ARM10 was released in 1999 and is designed mainly for high performance. It extends the ARM9 pipeline to 6 stages and also supports an optional vector floating point unit (VFP), which adds a seventh stage to the ARM10 pipeline. VFP significantly improves the performance of floating point operations and is compatible with the IEEE754.1985 floating point standard.
The ARM1020E is the first processor to use the ARM10E core. Like the ARM9E, it includes enhanced E instructions. It has an independent 32KB D+I 
cache, an optional vector floating point unit (VFP), and an MMU. The ARM1020E also has a dual 64-bit bus interface for improved performance.
The ARM1026EJ-S is very similar to the ARM926EJ-S, but has both an MPU and an MMU. This processor has the performance of the ARM10 and the flexibility of the ARM926EJ-S.

1.1.2.4 ARM11 series
ARM1136J-S was released in 2003 and is designed for high-performance and energy-efficient applications. ARM1136J-S is the first processor to execute ARMv6 architecture instructions. It integrates an 8-stage pipeline with independent load-store and arithmetic pipelines. ARMv6 instructions include single instruction multiple data (SIMD) extensions for media processing, specially designed to improve video processing performance.
ARM1136JF-S is designed for fast floating-point operations, and a vector floating-point unit is added to ARM1136J-S.

1.1.2.5 ARM Cortex Series
ARM Cortex was released in 2005, providing a complete set of optimized solutions for applications with different performance requirements. The technical division of this series is completely aimed at different market applications and performance requirements. Currently, ARM 
Cortex defines three series:

Cortex-A series: application processors for complex OS and applications (such as multimedia). Supports ARM, Thumb and Thumb-2 instruction sets, emphasizes high performance and reasonable power consumption, and memory management supports virtual addresses.

Cortex-R series: Embedded processors for real-time systems. Supports ARM, Thumb and Thumb-2 instruction sets, emphasizes real-time performance, and memory management only supports physical addresses.

Cortex-M series: Embedded processors for price-sensitive applications, only supports the Thumb-2 instruction set, emphasizes operational determinism, and balances between performance, power consumption, and price.

These series were formally introduced during the development of ARMv7, and the A series and R series had already appeared implicitly in early versions, as well as the Virtual Memory System Architecture (VMSA) and Protected Memory System Architecture (PMSA).
So far, the officially released versions of the Cortex series are Cortex-A8, Cortex-R4 and Cortex_M3, all of which implement the Thumb-2 instruction set (or subset) to meet different performance and price market requirements.

ARM 
Cortex-M3 does not support the ARM instruction set. The supported instruction sets include most of the 16-bit Thumb instructions of ARMv6 and the Thumb-2 instruction set of ARMv7. The Thumb-2 instruction set is a 16/32-bit mixed instruction system. The 16-bit and 32-bit Thumb instructions supported by Cortex-M3

To use a low-cost 32-bit processor , developers face two choices: processors based on the Cortex-M3 core or the ARM 7TDMI core. How to make a choice? What are the selection criteria? This article mainly introduces some characteristics of the ARM Cortex-M3 core microcontroller that are different from the ARM7 to help you make a quick choice.

　　1. ARM Implementation Method

　　ARM Cortex-M3 is the latest ARM embedded core based on ARM7v architecture. It adopts Harvard structure and uses separate instruction and data buses (under von Neumann structure, data and instruction share one bus). In essence, Harvard structure is more complex physically, but the processing speed is significantly faster. According to Moore's Law, complexity is not a very important thing, but the increase in throughput is extremely valuable.

　　ARM's positioning of Cortex-M3 is to provide low-cost, low-power chips to the professional embedded market. In terms of cost and power consumption, Cortex-M3 has quite good performance, and ARM believes that it is particularly suitable for the automotive and wireless communication fields. Like all ARM cores, ARM licenses the design to various manufacturers to develop specific chips. So far, several chip manufacturers have begun to produce microcontrollers based on Cortex-M3 cores.

　　The ARM7TDMI (including ARM7TDMIS) series of ARM cores are also aimed at the same market. This type of core has been around for more than ten years and has driven ARM to become the leader in the field of processor cores. Numerous manufacturers sell processors based on the ARM7 family, along with other supporting system software, development and debugging tools. In many ways, the ARM7TDMI is a doer in the embedded world.

　　2. Differences between the two

　　In addition to using the Harvard structure, the Cortex-M3 also has other significant advantages: a smaller basic core, lower price, and faster speed. Integrated with the core are some system peripherals, such as interrupt controllers, bus matrices, and debugging function modules, which are usually added by chip manufacturers. The Cortex-M3 also integrates a sleep mode and an optional complete eight-region memory protection unit. It uses the THUMB-2 instruction set to minimize the use of assemblers.

　　3. Instruction set

　　ARM7 can use both ARM and Thumb instruction sets, while Cortex-M3 only supports the latest Thumb-2 instruction set. The advantages of this design are:
　　● It eliminates the need to switch between Thumb and ARM code. For early processors, this state switching will reduce performance.
　　● The Thumb-2 instruction set is designed specifically for C language and includes If/Then structures (predicting the conditional execution of the next four statements), hardware division, and local bit field operations.
　　● The Thumb-2 instruction set allows users to maintain and modify applications at the C code level, and the C code part is very easy to reuse. ● The
　　Thumb-2 instruction set also includes the function of calling assembly code: Luminary believes that there is no need to use any assembly language.
　　● Combining the above advantages, the development of new products will be easier to implement and the time to market will be greatly shortened.

　　4. Interrupt

　　Another innovation of Cortex-M3 is the Nested Vector Interrupt Controller NVIC (Nested Vector Interrupt Controller). Compared with the external interrupt controller used by ARM7, the Cortex-M3 core integrates an interrupt controller, which can be configured by chip manufacturers to provide a basic 32 physical interrupts with 8 levels of priority, up to 240 physical interrupts and 256 interrupt priorities. This type of design is deterministic and has low latency, especially suitable for automotive applications.

　　NVIC uses a stack-based exception model. When processing an interrupt, the program counter, program status register, link register and general registers are pushed into the stack, and these registers are restored after the interrupt processing is completed. Stack processing is done by hardware, and there is no need to create stack operations for interrupt service routines in assembly language.
Interrupt nesting can be implemented. Interrupts can be changed to use a higher priority than the previous service routine, and the priority status can be changed at runtime. Using the tail-chaining continuous interrupt technology only consumes three clock cycles, which greatly reduces latency and improves performance compared to 32 clock cycles of continuous stack push and pop.

　　If the NVIC has pushed the stack before a higher priority interrupt arrives, it only needs to get a new vector address to service the higher priority interrupt. Likewise, the NVIC does not pop the stack to service the new interrupt. This approach is completely deterministic and has low latency.

　　5. Sleep

　　The power management scheme of Cortex-M3 supports three sleep modes through NVIC: Sleep Now, Sleep on Exit, (exit the lowest priority ISR) and SLEEPDEEP modes.

　　In order to generate regular interrupt time intervals, NVIC also integrates a system beat timer, which can also be used as a heartbeat for RTOS and scheduling tasks. This approach is different from the previous ARM architecture in that no external clock is required.

　　6. Memory Protection Unit

　　The Memory Protection Unit is an optional component. With this option, memory areas can be associated with application-specific processes according to the rules defined by other processes. For example, some memory can be completely blocked by other processes, while other parts of memory can be displayed as read-only for certain processes. It is also possible to prohibit processes from accessing memory areas. Reliability, especially real-time performance, is thus significantly improved.

　　7. Debugging

Debugging and tracing the Cortex-M3 processor system is achieved through the debug access port. The debug access port can be a 2-pin serial debug port (Serial Wire Debug Port) or a serial JTAG debug port (Serial Wire JTAG Debug Port). Through the combination of a series of functions such as Flash slice, breakpoint unit, data watchpoint, trace unit, and optional embedded trace macrocell (Embedded Trace Macrocell) and instruction trace macrocell (InstrumentaTIon Trace Macrocell), various types of debugging methods and monitoring functions can be used in the core part. For example, you can set breakpoints, watchpoints, define default conditions or execute debug requests, monitor stop operations or continue operations. All of these functions have been implemented in ARM architecture products, but Cortex-M3 integrates these functions for the convenience of developers.

　　8. Application Scope

　　Although the ARM7 core does not integrate as many peripherals as the Cortex series, a large number of ARM7-based devices, from general-purpose MCUs to application-oriented MCUs, SOCs and even Actel's ARM7-based FPGAs, have more peripherals. There are about 150 MCUs based on the ARM7 core (this number may be higher depending on different statistical methods).

　　You will find that ARM7 can implement almost all embedded applications, or use customized methods to meet the needs. Based on the standard core, chip manufacturers can add different types and sizes of memory and other peripherals, such as serial interfaces, bus controllers, memory controllers and graphics units, and use different chip packages for industrial, automotive or other demanding fields, and provide chip versions with different temperature ranges. Chip manufacturers may also bundle specific software, such as TCP/IP protocol stacks or software for specific applications.

　　For example, STMicroelectronics' STR7 product line has three main series with a total of 45 members, with different packages and memories. Each series targets a specific application field and has a different set of peripherals. For example, the STR730 family is designed for industrial and automotive applications, so it has an expandable temperature range, including multiple I/O ports and 3 CAN bus interfaces. The STR710 is aimed at the consumer market and high-end industrial applications. It has multiple communication interfaces, such as USB, CAN, ISO7816 and 4 UARTs, as well as large-capacity memory and an external memory interface.

　　Chip manufacturers can also choose measures that are beneficial to developers in developing products, such as using ARM's embedded trace macrocell ETM (Embedded Trace Macrocell) and providing development and debugging tools.

　　Luminary and STMicroelectronics already have chips based on Cortex-M3, and other companies such as NXP and Atmel have also announced the production of such products.

　　9. Supporting tools

　　ARM7 applications are already very popular, and it has a lot of third-party development and debugging tools to support it. There is a list of more than 130 tool companies on the ARM website.
　　
　　Most manufacturers provide basic development boards, and provide interfaces for downloading programs, debugging tools, and drivers for external devices, including LED light display status or single-line display on the screen. Usually, the development kit includes a compiler, some debugging software, and a development board. More advanced kits include third-party integrated development environments (IDEs), which include compilers, linkers, debuggers, editors, and other tools, and may also include simulation hardware, such as JTAG emulators. In-circuit emulators (ICEs) are one of the earliest and most useful forms of debugging tools, and many manufacturers provide this interface on ARM7.

　　Software development tools range from modeling to visual design to compilers. Many products now also use real-time operating systems (RTOS) and middleware to speed up the development process and reduce the difficulty of development. In addition, there is another very important factor. Many developers have rich experience in ARM7 development.
Although there are emerging Cortex-M3 tools now, there is obviously still a certain gap. However, the integrated debugging capabilities of the Cortex-M3 make debugging simple and effective without the need for an in-circuit emulator (ICE).

　　10. Decision

　　So, how should you make a choice? If cost is the main consideration, you should choose Cortex-M3; if you seek better performance and improved power consumption at a low cost, you'd better consider using Cortex-M3; especially if your application is in the automotive and wireless fields, it's best to use Cortex-M3, which is the main market for Coretex-M3.

　　Due to the multiple integrated elements in the Cortex-M3 core and the use of Thumb-2 instruction set, its development and debugging are simpler and faster than ARM7TDMI. However, since redefining the application of ARM7TDMI is not a difficult task, especially when using RTOS. Conservatives may continue to use chips with ARM7TDMI cores and avoid using functions that make redefinition complicated.

　　IAR Systems is the earliest manufacturer of C compilers and provides a series of ARM development tools, including IAR visualSTATE modeling tools, IAR Embedded Workbench for ARM integrated development environment, IAR PowerPac real-time operating system and middleware, J-Link hardware simulation tools and development kits. Whether the user's choice is ARM7 or Cortex-M3, IAR will make development easy and fun.