MSP430 Functional Module Detailed Explanation Series - FLASH Memory

1.8～3.6V working voltage, 2.7～3.6V programming voltage;
erasing/programming times can reach 100,000 times:
data retention time ranges from 10 years to 100 years:
60KB space programming time <5 seconds:
after the confidentiality fuse is burned out, it cannot be recovered and no access to JTAG can be made;
FLASH programming/erasing time is controlled by internal hardware without any software intervention;

2. Operation of FLASH memory

Since the FLASH memory is composed of many relatively independent segments, the program can be run in one segment while erasing or writing to another segment. The FLASH segment that is performing programming or erasing operations cannot be accessed because the segment is temporarily disconnected from the on-chip address bus.

The operations on the FLASH module can be divided into three categories: erase, write and read. Erasing can be divided into single-segment erase and entire module erase; writing can be divided into word write, byte write, word continuous write and byte continuous write.

1. FLASH erase operation: To write data to FLASH, you must first erase the corresponding segment. The FLASH memory must be erased in its entirety. You can erase it segment by segment or multiple segments at once, but not one byte or one word at a time. After erasing, each bit is 1. The order of the erase operation is as follows:

Select the appropriate clock source and frequency division factor to provide the correct clock input for the timing generator.
If Lock=1, reset
the BUSY flag. Only when BUSY=0 can the next step be executed, otherwise it will always be BUSY.
If erasing a segment, set ERASE=1.
If erasing multiple segments, set MERAS=1.
If erasing the entire FLASH, set RASE=1. At the same time, MERAS=1
will write a blank to any location within the erased address range to start the erase operation.
The clock source selected during the erase cycle is always valid .
The frequency division factor is not modified during the erase cycle. The
segment being operated is no longer accessed during BUSY=1.
The power supply voltage should meet the corresponding requirements of the chip.

There are 4 things to do to erase FLASH

Write the appropriate control bit to the FLASH control register
****BUSY bit
Write once
Wait

2. FLASH programming operation. FLASH programming is performed in the following order:

Select the appropriate clock source and frequency division factor
If Lock=1, reset
the BUSY flag. Only when BUSY=0 can the next step be executed, otherwise it will always be BUSY.
If writing a single word or a single byte, set WRT=1.
If it is a block write or a multi-word or multi-byte sequential write, set WRT=1, BLKWRT=1.
Start the timing generator when writing data to the selected address, and complete the entire process under the control of the timing generator.

Block write can be used to write a series of data in a continuous storage area in the FLASH segment. A block is 64 bytes long. The block starts at addresses 0XX00H, 0XX40H, 0XX80H, 0XXC0H, etc., and ends at addresses 0XX3FH, 0XX7FH, 0XXBFH, 0XXFFH, etc. Block operations require special software support at the 64-byte boundary, and the operation is as follows:

Wait for the WAIT bit until WAIT=1, indicating the end of the last word or byte write operation.
Reset the control bit BLKWRT.
Keep the BUSY bit at 1 until the programming voltage is removed from the FLASH module
. Wait for trcv (programming voltage recovery time) before the new block is programmed.

During the write cycle, the following conditions must be met:

The selected clock source remains valid during the write process.
The frequency division factor remains unchanged.
The FLASH memory module is not accessed during BUSY=1.

There are 4 things to do when writing to FLASH

Write the appropriate control bit
****BUSY bit to the FLASH control register
Write a data
Continue writing until the writing is completed

3. Handling of FLASH error operation: When writing the control parameters of the FLASH control register, the following errors may occur:

If the high byte password code is written incorrectly, the PUC signal will be triggered. Careful operation can avoid
Reading the FLASH content during FLASH operation will trigger the setting of the ACCVFIG status bit. Careful operation can avoid
Watchdog timer overflow during FLASH operation. It is recommended that the user program stop the watchdog timer before performing FLASH operation, and then turn on the watchdog after the operation is completed
All FLASH type MSP430 devices have important program codes such as interrupt vectors in segment 0. If they are erased, serious consequences will occur
Do not allow interrupts to occur during FLASH operation

4. Summary of FLASH operation

The operation of FLASH is completed by the corresponding bits in the three control words. Only the unique combination of control bits can realize the corresponding function. The following table gives the correct control bit combination:

3. FLASH register description

To allow programming, erasing, etc., the first thing to do is to define each bit of the three control registers (FCTL1, FCTL2, FCTL3). They use security key values ​​(password codes) to prevent incorrect programming and erasing cycles. Password errors will generate non-maskable interrupt requests. The security key value is located in the high byte of each control word, which is 96H when reading and 5AH when writing.

1. FCTL1 control register 1 (used to control the valid bits of all write/program or delete operations), each bit is defined as follows:

BLKWRT——Segment programming bit. If there are more continuous data to be programmed into a certain segment or several segments, this method can be selected to shorten the programming time. After a program is completed, the bit needs to be reset and then set before programming other segments. The WAIT bit should be 1 before the next write instruction is executed.

0: Segment programming is not selected
1: Segment programming is selected

WRT - Programming Bit

0: Do not program. If an illegal access occurs during a FLASH write operation, the ACCVIFG bit will be set.
1: Program

MERAS——Main Memory Control Erase Bit

0: Do not erase
1: Erase all main memory. When writing to the main memory, the erase operation is started. After completion, MERAS automatically resets

ERASE——Erase a section of control bits

0: Do not erase
1: Erase a segment. The segment number is entered by the empty write instruction to specify which segment to erase. It will automatically reset after the operation is completed.

2. FCTL2 control register 2 (defines the clock entering the timing generator), each bit is defined as follows:

SSEL1, SSEL0——Select clock source

0: ACLK
1: MCLK
2: SMCLK
3: SMCLK

FN5～FN0——Frequency division coefficient selection bit

0: Direct
1: 2-way
2: 3-way
......
63: 64-way

3. FCTL3 control register 3 (used to control FLASH memory operation and save corresponding status flags and error conditions), each bit is defined as follows:

EMEX——Emergency Exit Bit. Use this bit for emergency processing when the FLASH operation fails.

0: No effect
1: Immediately stop the operation of FLASH

Lock——Lock bit, lock the programmed FLASH memory

0: Unlocked, the FLASH memory is readable, writable, and erasable
1: Locked, the locked FLASH memory is readable, not writable, and not erasable

WAIT——Wait indication signal, this bit is read-only.

0: Segment programming operation has started and programming operation is in progress
1: Segment programming operation is valid, the current data has been correctly written into the FLASH memory, and the subsequent programming data is included in the plan

ACCVIFG - illegal access interrupt flag. When programming or erasing the FLASH array, the FLASH cannot be accessed, otherwise this bit will be set.

0: No illegal access to the FLASH memory
1: There is illegal access to the FLASH memory

KEYV——Security key value (password code) error flag

0: Access to 3 control registers, the high byte is 0A5H when writing
1: Access to 3 control registers, the high byte is not 0A5H when writing, and the PUC signal
KEYV will not be automatically reset and must be reset by software

BUSY - Busy flag. This bit is read-only. The BUSY bit should be checked before each programming or erasing. When programming or erasing is started, the timing generator will automatically set this bit to 1, and the BUSY bit will automatically reset after the operation is completed.

0: FLASH memory is not busy
1: FLASH memory is busy