When the operating voltage of the S3C2440 CPU core is 1.2V, the main frequency can reach 300MHz; when the operating voltage is 1.3V, the main frequency can reach 400MHz. The development board is 12MHz, and the system clock needs to be increased through the PLL of the clock control logic.
S3C2440 has two PLLs: MPLL and UPLL. UPLL is dedicated to USB devices, and MPLL is used to set FCLK, HCLK, and PCLK.
Where m=MDIV+8, p=PDIV+2, s=SDIV
CLKDIVN register: used to set the ratio of FCLK, HCLK, and PCLK. The register settings corresponding to various clock ratios are shown in the figure below:
program is analyzed as follows: (This program is from Professor Zhao Chunjiang)
#include "2440addr.h"
#define U32 unsigned int
typedef unsigned char BOOL;
#define TRUE 1
#define FALSE 0
BOOL stop;
static void __irq Key3_ISR(void) /*Pause key, turn off the buzzer*/
{
rSRCPND = rSRCPND | (0x1<<2); /*define EINT2*/
rINTPND = rINTPND | (0x1<<2);
rTCON &= ~0x8; /*Disable timer automatic reload, that is, turn off timer 0111*/
stop = TRUE;
}
void __irq Key2_ISR(void) /*Restart key, turn on the buzzer*/
{
rSRCPND = rSRCPND | 0x1; /*define EINT0*/
rINTPND = rINTPND | 0x1;
stop = FALSE;
}
void delay(int a)
{
int k;
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