Implementation of s3c6410 timer interrupt

five 32-bit timers
Timers 0 and 1 include a PWM function

Each timer has its own 32-bit down-counter which is driven by the timer clock. The down-counter is initially loaded
from the Timer Count Buffer register (TCNTBn). When the down-counter reaches zero, the timer interrupt request
is generated to inform the CPU that the timer operation is completed. When the timer down-counter reaches zero,
the value of corresponding TCNTBn can be automatically reloaded into the down-counter to start the next cycle.
However, if the timer stops, for example, by clearing the timer enable bit of TCONn during the timer running mode,
the value of TCNTBn will not be reloaded into the counter.

1 Timer 0 related registers
 
 1) TCON timer control register (related to timer0 [3:0], switch, manual update of initial value, automatic reload of initial value (
 when TCNT0 is reduced to 0, it is automatically loaded from TCNTB0 to TCNT0) etc.)

 
 2) TCNTB0 stores the initial value of timer0;
    TCMPB0 stores the value to be compared by timer0 (the default is 0, then tcnt0 is compared with tcmp0)
 3) TINT_CSTAT Interrupt Control And Status Register) There are two bits related to timer interrupt control and timer0, [0] bit Timer 0 Interrupt Enable.
  [5] bit Timer 0 Interrupt Status Bit. Clears by writing '1' on this bit. (This bit needs to be cleared by writing 1 in ISR)
 4) TCFG0 Timer Configuration Register 0 that configures thetwo 8-bit Prescaler and DeadZone Length
  sets the division factor of each timer. The lower eight bits are related to timer0 and timer1.
 5) VIC0INTENABLE interrupt enable control (32 bits correspond to 32 interrupt sources (note that it is VIC0 group, timer0 is at 23 bits)

2Timer0 related register settings 

Because an auto-reload operation of the timer occurs when the down counter reaches to 0, a starting value of the
TCNTn has to be defined by the user at first. In this case, the starting value has to be loaded by the manual
update bit . Take the following steps to start a Timer;
1) Write the initial value into TCNTBn and TCMPBn.
2) Set the manual update bit of the corresponding timer.
(Recommended setting the inverter on/off bit (whether using inverter or not)) .
3) Set the start bit of the corresponding timer to start the timer and clear only manual update bit.

timer0 init function in main.c
void timer_init(void)
{
 TINT_CSTAT |= 1<<0; //Open timer0 interrupt, allow timer0 interrupt to occur
 VIC0INTENABLE |= 1<<23; //Open timer0 enable (equivalent to turning off mask)
 TCFG0 = 0x42; //Set the frequency division factor
 
 TCNTB0 = 0x1000; //Set the initial value
 TCON |= 1<<1; //Open Manual Update (Update TCNTB0,TCMPB0) and update TCNTB after setting the initial value
 TCON |= 1<<3; 、、//Auto Reload on Automatic reload on
 TCON |= 1<<0; //timer0 open;
 
 TCON &= ~(1<<1); 、//No longer Update TCNTB0,TCMPB0

 
} Handler irq_handler
in start.s  ;push rets to stack  stmfd sp!,{r0-r12,lr}  ;handler  bl do_timer_irq //jump to related execution function  ;pop stack to regs  ldmfd sp!, {r0-r12,lr}  subs pc, lr,#4



 

The following is similar to external interrupts.
When timer0 interrupt occurs, the program goes to the entry 0x18 of the IRQ exception vector table, where the program jumps to IRQ_handler(); in the interrupt service function (ISR), it is necessary to write 1 to clear 0 to the 5th bit of TCON at the beginning; for the next interrupt