Explanation of four methods of ARM GPIO port

From the characteristics of the I/O port, the P0 port of the standard 80C51 is an open-drain structure when used as an I/O port, and a pull-up resistor is usually added in actual applications; P1, P2, and P3 are all quasi-bidirectional I/O ports with internal pull-up resistors, which can be used as both input and output. The I/O port characteristics of the LPC900 series microcontrollers are somewhat different, and they can be configured into 4 different working modes: quasi-bidirectional I/O, push-pull output, high-impedance input, and open-drain.

Compared with the standard 80C51, the quasi-bidirectional I/O mode is different in internal structure, but similar in usage. For example, to use it as an input, you must first write "1" to set it to a high level before you can read the pin's level status.

The characteristic of push-pull output is that it can drive a large current regardless of whether the output is high or low. For example, when the output is high, the LED can be directly lit (with a current-limiting resistor of several hundred ohms connected in series), which is difficult to do in quasi-bidirectional I/O mode.

The characteristic of high-impedance input mode is that it can only be used as an input, but a relatively high input impedance can be obtained, which is necessary in analog comparator and ADC applications.

The open-drain mode is similar to the quasi-bidirectional mode, but there is no internal pull-up resistor. The advantage of the open-drain mode is good electrical compatibility. If the external pull-up resistor is connected to a 3V power supply, it can interface with a 3V logic device. If the pull-up resistor is connected to a 5V power supply, it can interface with a 5V logic device. In addition, the open-drain mode can also easily implement the "wired AND" logic function.

1. High impedance input (Input)

In order to reduce the number of information transmission lines, the information transmission lines in most computers adopt the bus form, that is, all the same type of information to be transmitted is in the same group of transmission lines, and the information is transmitted in time. In computers, there are generally three groups of buses, namely data bus, address bus and control bus. In order to prevent information from interfering with each other, it is required that the input and output ends of all registers or memories connected to the bus can not only present two information states of 0 and 1, but also a third state-high impedance state, that is, at this time, it seems that their outputs are disconnected by switches and have no effect on the bus state. At this time, the bus can be occupied by other devices. The tri-state buffer can realize the above function. In addition to the input and output ends, it also has a control end.
       As shown in Figure 1.1, it is a schematic diagram of the equivalent structure of the GPIO pin in the high-impedance input mode. This is the case of this pin, and the structure of other pins is the same. The structure of the input mode is relatively simple, that is, a tri-state buffer (U1) with Schmitt-triggered input and a very high input equivalent impedance. The function of Schmitt trigger input is to shape the slowly changing or distorted input pulse signal into a relatively ideal rectangular pulse signal. When performing a GPIO pin read operation, the current level state of the pin (Pin) will be read to the internal bus (Internal Bus) under the action of the read pulse (Read Pulse). When not performing a read operation, the external pin is isolated from the internal bus.

2. Push-pull output (Output)

  Push-pull output principle: Push-pull amplifier circuits are widely used in power amplifier circuits. In this circuit, two transistors are used to form a first-stage amplifier circuit. The two transistors amplify the positive half cycle and negative half cycle of the input signal respectively, that is, one transistor amplifies the positive half cycle of the signal, and the other transistor amplifies the negative half cycle of the signal. The half-cycle signals output by the two transistors are combined on the amplifier load to obtain a complete cycle output signal.
     In the push-pull amplifier circuit, when one transistor is working in the on-state and amplification state, the other transistor is in the off-state. When the input signal changes to another half cycle, the transistor that was originally on and amplified enters the cut-off state, and the transistor that was originally cut-off enters the on-state and amplification state. The two transistors are constantly alternating between on-state, amplification and cut-off, so it is called a push-pull amplifier (armjishu.com).
        As shown in Figure 1.2, it is a schematic diagram of the equivalent structure of the GPIO pin in push-pull output mode. U1 is an output latch. When the GPIO pin write operation is executed, the data is latched into Q and /Q under the action of the write pulse. T1 and T2 form a CMOS inverter. When T1 is turned on or T2 is turned on, it shows a low impedance, but T1 and T2 will not be turned on or off at the same time, and the final result is a push-pull output. In the push-pull output mode, the GPIO also has a readback function, and a simple three-state gate U2 is used to implement the readback function. Note: When the readback function is executed, the output latch state of the pin is read, not the state of the external pin Pin.

3. Open-drain output (OutputOD)

As shown in Figure 1.3, it is a schematic diagram of the equivalent structure of the GPIO pin in the open-drain output mode. The open-drain output has a basically the same structure as the push-pull output, but only has a pull-down transistor T1 and no pull-up transistor. Similarly, T1 is actually a group of programmable selectable transistors. The actual function of the open-drain output is a switch, which is disconnected when outputting "1" and connected to GND (with a certain internal resistance) when outputting "0". Readback function: What is read is still the state of the output latch, not the state of the external pin Pin. Therefore, the open-drain output mode cannot be used for input. The
        open-drain output structure has no internal pull-up, so in actual application, it is usually necessary to connect a suitable pull-up resistor (usually 4.7~10kΩ). The open-drain output can easily realize the "wired AND" logic function, that is, multiple open-drain pins can be directly connected together (no buffer isolation is required) and connected to a suitable pull-up resistor, which naturally forms a "logical AND" relationship. Another use of open-drain output is to easily achieve conversion between different logic levels (such as 3.3V to 5V), only need an external pull-up resistor, without additional conversion circuit. A typical application example is the I2C bus based on open-drain electrical connection.

4. Clamping diode

GPIO has a clamping protection diode inside, as shown in Figure 1.4. Its function is to prevent the voltage input from the external pin Pin from being too high or too low. The normal power supply of VDD is 3.3V. If the voltage of the signal input from Pin (assuming that any input signal has a certain internal resistance) exceeds VDD plus the conduction voltage drop of diode D1 (assuming it is around 0.6V), then diode D1 will be turned on, which will lead the excess current to VDD, and the actual signal voltage input to the internal will not exceed 3.9V. Similarly, if the signal voltage input from Pin is lower than GND, due to the effect of diode D2, the actual signal voltage input to the internal will be clamped at around -0.6V.

 

Assuming VDD = 3.3V, GPIO is set in open-drain mode, and an external 10kΩ pull-up resistor is connected to a 5V power supply. When outputting "1", we found through measurement that the voltage on the GPIO pin does not reach 5V, but is around 4V. This is where the internal clamping diode comes into play. Although the output voltage does not reach the full 5V, for actual digital logic, 3.5V or above is usually considered a high level (armjishu.com).

 

If you really want to further increase the output voltage, a simple way is to first connect a diode (such as 1N4148) in series with the GPIO pin, and then connect a pull-up resistor. See Figure 1.5, the box is the internal circuit of the chip. When writing "1" to the pin, T1 is turned off, and the voltage obtained at the pin is 3.3 + VD1 + VD3 = 4.5V, and the voltage boost effect is obvious; when writing "0" to the pin, T1 is turned on, and the voltage obtained at the pin is VD3 = 0.6V, which is still a low level.