How to achieve 0.125ns dynamic delay

小白111

How to achieve 0.125ns dynamic delay [Copy link]

Dynamically adjust the delay, each step is 0.125ns

chunyang

The expression of 0.125nS indicates that the precision requirement is extremely high, which is three orders of magnitude smaller than the nS level. This cannot be achieved by circuit means, at least I think it is impossible. I am afraid it can only be achieved by optical means, but the interface with the circuit is still an extremely difficult challenge. In this case, I doubt whether the reason for your indicator is valid. What is the application?

daemondong

It is estimated that it can only be realized using FPGA

heningbo

This is equivalent to 8G. The only signals of this rate that I have seen are some serdes signals, but nothing else.

book1

Are there any FPGA chips with clock designs that can reach 1ns? Thank you!

刘飞飞_111

Take a look at the carry chain of FPGA?