ARM register summary

 r15 acts as the program register PC, r14 (link register) stores the return address of the subroutine, and r13 stores the stack address.

ARM has a current program status register: CPSR.

Some registers (r13, r14) will generate new instances when an exception occurs, such as IRQ processor mode, when the processor uses r13_irq and r14_irq

 ARM's subroutine calls are very fast because the subroutine's return address does not need to be stored on the stack.

1.  The ARM processor has a total of 37 registers, including:

i. 31 general purpose registers, including the program counter (PC). All are 32-bit registers

ii. 6 status registers, all 32-bit registers, but only 12 bits are currently used

2.  ARM processors have 7 different processor modes, and each processor mode has a corresponding register group. At any time (that is, in any processor mode), the visible registers include 15 general registers (R0~R14), one or two status registers and the program counter (PC). Among all the registers, some are the same physical registers shared by all modes, and some are independent physical registers owned by each mode.

3.  General registers can be divided into three categories: unbacked registers (R0~R7), backup registers (R8~R14) and program counter PC (R15). For each unbacked register, it refers to the same physical register in all processor modes. For backup registers R8~R12, each register corresponds to two different physical registers, which makes interrupt processing very simple. For example, when only R8~R14 registers are used, the FIQ handler does not need to execute instructions to save and restore the interrupt scene, making the interrupt processing process very fast. For backup registers R13 and R14, each register corresponds to 6 different physical registers, one of which is shared by user mode and system mode, and the other 5 correspond to the other 5 processor modes.

4.  Each exception mode has its own physical R13. The application initializes R13 to point to the stack address dedicated to the exception mode. When entering the exception mode, the registers to be used can be saved in the stack pointed to by R13; when exiting the exception handler, the register values ​​saved in the stack pointed to by R13 are popped out. In this way, the exception handler will not destroy the running scene of the interrupted program.

5.  Register R14 is also called Link Register (LR), which has the following two special functions in the ARM system:

i.  Each processor mode stores the return address of the current subroutine in its own physical R14. When a subroutine is called through a BL or BLX instruction, R14 is set to the return address of the subroutine. In the subroutine, when the value of R14 is copied to the program counter PC, the subroutine returns.

ii.  When an exception interrupt occurs, the physical R14 specific to the exception mode is set to the address to be returned by the exception mode. For some exception modes, the value of R14 may have a constant offset from the address to be returned. The specific return method is basically the same as the subroutine return method.