Introduction to ARM registers-EEWORLD

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The ARM processor contains 37 registers, which include the following two types of registers.

(1) 31 general registers: including the program counter PC, etc. These registers are all 32-bit registers.

(2) 6 status registers: The status register is also a 32-bit register, but only 12 bits are used.

1. General registers
Each of the 7 modes of the ARM processor has a corresponding register group. At any time, the visible register group includes 15 general registers R0 to R14, one or two status registers and PC. Among all the registers, some are the same physical registers shared by various modes, and some are physical registers owned by each mode independently. Details are shown in Table 1-3.

Table 1-3 ARM physical registers

User Mode	System Mode	Privileged Mode	Abort Mode	Undefined instruction mode	External interrupt mode	Fast interrupt mode
R0	R0	R0	R0	R0	R0	R0
R1	R1	R1	R1	R1	R1	R1
R2	R2	R2	R2	R2	R2	R2
R3	R3	R3	R3	R3	R3	R3
R4	R4	R4	R4	R4	R4	R4
R5	R5	R5	R5	R5	R5	R5
R6	R6	R6	R6	R6	R6	R6
R7	R7	R7	R7	R7	R7	R7
R8	R8	R8	R8	R8	R8	R8_fiq
R9	R9	R9	R9	R9	R9	R9_fiq
R10	R10	R10	R10	R10	R10	R10_fiq
R11	R11	R11	R11	R11	R11	R11_fiq
R12	R12	R12	R12	R12	R12	R12_fiq
R13	R13	R13_svc	R13_abt	R13_und	R13_irq	R13_fiq
R14	R14	R14_svc	R14_abt	R14_und	R14_irq	R14_fiq
PC	PC	PC	PC	PC	PC	PC
CPSR	CPSR	CPSR	CPSR	CPSR	CPSR	CPSR
		SPSR_svc	SPSR_abt	SPSR_und	SPSR_irq	SPSR_fiq

General registers can usually be divided into the following three categories.

nUnbacked up registers: including R0~R7.

nBackup registers : including R8~R14.

nProgram counter PC: that is, R15.

1) Registers R0 to R7 are not backed up

For each unbacked register, it refers to the same physical register in all processor modes. When the processor mode is switched due to an abnormal interrupt, the data in the register may be destroyed because different processor modes use the same physical register. Unbacked registers are not used for special purposes by the system. Any application that can use general registers can use unbacked registers.

2) Backup registers R8~R14

Each register in the backup register corresponds to two different physical registers. For example, when using the registers in fast interrupt mode, register R8 and register R9 are recorded as R8_fiq and R9_fiq respectively. When using the registers in user mode, register R8 and register R9 are recorded as R8_usr and R9_usr respectively. Different physical registers are used in these two cases, and the system does not use these registers for any special purpose. Interrupt processing is very simple. When only registers R8 to R14 are used, the FIQ handler does not need to execute instructions to save and restore the interrupt scene, which can make the interrupt processing process very fast.

For the backup registers R13 and R14, each register corresponds to 6 different physical registers, one of which is shared by the user mode and the system mode, and the other 5 correspond to the other 5 processor modes, which are identified using the following method.

R13_,

Among them are usr, svc, abt, und, irq and fiq.

R13 is usually used as a stack pointer. Each mode has its own physical R13. The program initializes R13 to point to the stack address dedicated to the mode. When entering the mode, the registers to be used can be saved in the stack pointed to by R13. When exiting the mode, the register values saved in the stack pointed to by R13 are popped out. In this way, the program's on-site protection is achieved.

① Each processor mode stores the return address of the current subroutine in its own physical R14. When a subroutine is called through a BL or BLX instruction, R14 is set to the return address of the subroutine. In the subroutine, when the value of R14 is copied to the program counter PC, the subroutine return is realized.

The return operation of this subroutine can be implemented in the following two ways.

◆Execute any of the following instructions

MOV pc, LR

BX LR

◆Use the following instruction at the subroutine entry to save the PC to the stack:

STMFD SP!, {registers}, LR}

Accordingly, the following instructions can realize the return of the subroutine:

LDMFD SP!, { registers}, LR }

② When an exception occurs, the specific physical R14 in this mode is set to the address to which the exception mode will return. For some exceptions, the value of R14 may have a constant offset from the address to be returned. The specific return method is basically the same as the subroutine return method above.

3) Program counter PC → R15

The program counter R15 is also called PC. Although it can be used as a general register, some instructions have some special restrictions when using R15. When these restrictions are violated, the result of the instruction execution will be unpredictable.

Since ARM uses a pipeline mechanism, when the value of PC is correctly read, the value is the current instruction address value plus 8 bytes. That is to say, for the ARM instruction set, PC points to the address of the next two instructions of the current instruction. Since ARM instructions are word-aligned, the 0th and 1st bits of the PC value are always 0. It
should be noted that when using the instruction STR/STM to save R15, it may be the current instruction address value plus 8 bytes, or it may be the current instruction address plus 12 bytes. Which method is used depends on the specific design of the chip. In any case, in the same chip, either the current instruction address plus 8 or the current instruction address plus 12 is used. It is not possible for some instructions to use the current instruction address plus 8 and other instructions to use the current instruction address plus 12. Therefore, for users, try to avoid using STR/STM instructions to save the value of R15. When this method is unavoidable, you can first use some codes to determine which implementation method the chip used uses.

Assuming R0 points to an available memory word, the following code can return the address offset used by the chip in the memory word pointed to by R0.

SUB R1, PC, #4 ;R1 stores the address of the following STR instruction

STR PC, [R0] ; Save PC = STR address + offset to R0

LDR R0, [R0] ;

SUB R0, R0, R1 ;offset=PC-STR address

2. The program status register
CPSR (Current Program Status Register) can be accessed in any processor mode. Each mode has a dedicated physical status register called SPSR (Backup Program Status Register). When a specific exception interrupt occurs, this register is used to store the contents of the current program status register. When an exception exits, the CPSR can be restored with the value saved in SPSR. The specific format of CPSR is as follows.

31	30	29	28	27	26	7	6	5	4	3	twenty one	0
N	Z	C	V	Q	DNMLRAZ	I	F	I	M4	M3	M	M0

1) Condition flag

N (Negative), Z (Zero), C (Carry) and V (overflow) are collectively referred to as conditional flags. Most ARM instructions can be selectively executed based on these flags in the CPSR. The specific meanings of each conditional flag are shown in Table 1-4.

Table CPSR flag meaning

Flags	meaning
N	This bit is set to the value of bit [31] of the current instruction operation result. When a two's complement signed integer is used for an operation, N = 1 indicates that the result of the operation is a negative number, and N = 0 indicates that the result is a positive number or zero.
Z	Z＝1 means the result of the operation is 0, Z＝0 means the result of the operation is not zero For the CMP instruction, Z=1 means that the two numbers being compared are equal.
C	In addition instructions (including comparison instructions CMN), if the result produces a carry, C = 1, indicating that an overflow occurs in the unsigned number operation. In other cases, C = 0 In the subtraction instruction (including the comparison instruction CMP), if the result is a borrow, C = 0, indicating that the unsigned number operation has overflowed. In other cases, C = 1 For non-addition/subtraction instructions that include shift operations, C contains the value of the last overflowed bit. For other non-addition/subtraction instructions, the value of the C bit is usually not affected.
V	For addition/subtraction instructions, when the operands and the operation results are signed numbers represented by binary complement, V=1 indicates a sign bit overflow. Other instructions usually do not affect the V bit

2) Q flag

In the ARM v5 E series processors, bit [27] of CPSR is called the Q flag, which is mainly used to indicate whether an overflow has occurred in the enhanced DSP instruction. Similarly, bit [27] of SPSR is also called the Q flag, which is used to save and restore the Q flag in CPSR when an abnormal interrupt occurs.

3) Control bits in CPSR

The lower 8 bits I, F, T and M[4:0] of CPSR are collectively called control bits. These bits change when an abnormal interrupt occurs. In the privileged processor mode, the software can modify these control bits.

① I interrupt disable bit

When I=1, IRQ interrupt is disabled.

When F=1, FIQ interrupt is disabled.

Usually, once entering the interrupt service routine, interrupts can be disabled by setting I and F, but the original values of I and F bits must be restored before exiting the interrupt service routine.

② T control bit is used to control the status of instruction execution, that is, to indicate whether the instruction is an ARM instruction or a Thumb instruction. The meaning of the T control bit is slightly different for different versions of ARM processors.

For ARM v3 and lower processors and non-T series versions of ARM v4, there is no switch between ARM and Thumb instructions, so T is always 0.

For ARM v4 and later T-series processors, the T control bits have the following meanings.

When T=0, it means executing ARM instructions.

When T=1, it means executing Thumb instructions.

For ARM v5 and later non-T series processors, the meaning of the T control bit is as follows.

When T=0, it means executing ARM instructions.

When T=1, it means forcing the next instruction to be executed to generate a defined instruction interrupt.

③ M control bit

The control bit M[4:0] is called the processor mode identification bit, and its specific description is shown in Table 1-5.

Table CPSR processor mode bits

M[4:0]	Processor Mode	Accessible registers
0b10000	User	PC, R14～R0, CPSR
0b10001	FIQ	PC,R14_fiq～R8_fiq,R7～R0,CPSR,SPSR_fiq
0b10010	IRQ	PC,R14_irq～R13_irq,R12～R0,CPSR,SPSR_irq
0b10011	Supervisor	PC,R14_svc～R13_svc,R12～R0,CPSR,SPSR_svc
0b10111	Abort	PC,R14_abt～R13_abt,R12～R0,CPSR,SPSR_abt
0b11011	Undefined	PC,R14_und～R13_und,R12～R0,CPSR,SPSR_und
0b11111	System	PC, R14~R0, CPSR (ARM v4 and later)

④The other bits of CPSR are used for future expansion of ARM versions, and the program does not need to operate these bits for now.

Keywords：ARM Reference address：Introduction to ARM registers

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