Design principles of fuel gauge circuit based on BQ40z80

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Design principles of fuel gauge circuit based on BQ40z80 [Copy link]

1. Introduction

BQ40z80 is a fully integrated 2-7 lithium-ion or lithium polymer battery management chip, using the patented Impedance Track technology, with comprehensive programmable protection functions such as current, voltage and temperature. Its hardware circuit design is mainly divided into three parts: main current loop module, fuel gauge module and protection module.

2. Main current loop
The main current loop refers to the current loop that charges and discharges the battery under the control of the fuel gauge. When charging, the current in this loop starts from PACK+, passes through the switch FETs, chemical fuses, batteries and current sampling resistors used to control charging and discharging, and finally returns to PACK-.

2.1 Charge and discharge FETs
The two N-CH FETs for charge and discharge are connected in series with the PACK+ and the positive electrode of the battery pack in a drain-to-drain manner, as shown in Figure 2-1. Q2 and Q3 are charge and discharge FETs, respectively. When charging or discharging, Q2 and Q3 are turned on at the same time; when charging stops, Q2 is turned off; when discharging stops, Q3 is turned off.

Figure 2-1 MOSFET circuit diagram for charge, discharge, pre-charge, and pre-discharge.
When selecting FETs, the following two points should be noted: (1) The rated voltage of the FET must be greater than the maximum voltage of the battery; (2) Considering the back electromotive force generated at the load end during discharge, the rated voltage of the discharge FET should be slightly larger than that of the charging FET.

The typical values of gate drive resistance on the driving signals CHG and DSG are 1kΩ and 4.02kΩ respectively. The difference in resistance is determined by the internal structure of the pins, which makes the turn-on time of FETs about a few milliseconds. The typical value of the gate-source resistance of FETs is 10MΩ to ensure that FETs are turned off when the gate is open to avoid false turn-on.

The capacitors C1 and C2 connected across the FTEs protect the FETs in ESD events. The paths at both ends should be designed to be as short and wide as possible. At the same time, it should be noted that the rated voltages of C1 and C2 should be greater than the corresponding maximum voltage of the system, so that when one is short-circuited, the other can still play a protective role.

2.2 Pre-charge and pre-discharge FETs

The pre-charge function means that when the voltage at both ends of the battery is too low due to over-discharge, self-discharge due to long-term storage, etc., if the normal charging mode is directly entered, it is easy to damage the battery or affect the battery life. At this time, the pre-charge function is required to charge the battery to the normal voltage range with a small current and then switch to the normal charging mode. It is achieved by controlling the P-FET. The size of the pre-charge current is set by the current limiting resistor R2=(VCHARGER-VBAT)/R2, while taking into account the heat consumption P=(VCHARGER-VBAT)2/R2 on the resistor.

The pre-discharge function means that when the battery is applied to a large capacitive load, a transient surge current is easily generated at the moment of startup, and it is necessary to charge slowly in the form of soft start to reduce the instantaneous large current. As shown in Figure 1-1, the drive signal from Pins 16, 17 or 20 provides a high level to turn on the N-CH FET Q10, thereby connecting the gate of the pre-charge P-CH FET Q8 to the ground, turning on Q8, and opening the pre-charge circuit. Its pre-discharge rate is set by the current limiting circuit.

2.3 Anti-reverse connection protection

Reverse connection of the charger will cause great damage to the system, so a corresponding protection circuit needs to be designed for this purpose, as shown in Figure 2-2.

Figure 2-2 Reverse connection protection circuit

Without this protection, when a slightly smaller negative signal appears on PACK+, the discharge FET will enter the linear working area, affecting the normal operation of the circuit. However, after adding the anti-reverse connection circuit, the negative signal on PACK+ will turn on the N-FET Q9 with the gate grounded, short-circuiting the gate and source of the discharge FET, thereby playing a protective role. When selecting, you should choose an N-FET with a lower Vgs(th) to achieve a reliable and timely protection effect.

2.4 Battery input

BQ40z80 can manage and protect 2-7 lithium batteries. For 2-6 batteries, the chip contains an integrated voltage balancing module. You only need to connect them normally and short-circuit the unused pins. For example, as shown in Figure 2-3, VC6 and VC5 need to be short-circuited in the application of 5 series batteries. At the same time, an RC filter circuit should be designed for the input of each battery cell, which can not only play an ESD protection role, but also realize preliminary filtering of the input voltage signal. Considering that the resistor is in the voltage balancing loop, the resistance value should be balanced between the internal voltage balancing and the filtering frequency.

Figure 2-3 5-cell input connection method

For a 7-cell battery, additional settings are required to set the voltage balancing externally. The connection method is shown in Figure 2-4, where Pin VC7EN enables the voltage measurement of 7P.

Figure 2-4 7-cell connection method and external voltage balancing module

2.5 Current sampling resistor

The loop current value and direction determined by the sampling resistor are important input signals for the fuel gauge. The BQ40z80 has an integrated delt-sigma ADC for current detection, and the achievable measurement range is -0.1V to 0.1V. The voltage drop across the sampling resistor detected by Pins SRP and SRN determines the current flowing through the battery. On the one hand, it is used to determine whether the system is in charging or discharging mode. When VSR=V(SRP)-V(SRN) is detected to be a positive value, the system is in charging state, otherwise it is in discharging state; on the other hand, the accumulated charge obtained by the coulomb counter is one of the key parameters for fuel calculation.

The recommended sampling resistor value for BQ40z80 is 1mΩ-3mΩ. For high current applications, parallel sampling resistors are supported under the premise of ensuring reliable Kelvin connection. To prevent the high current under short circuit conditions from causing the voltage across the resistor to exceed the maximum absolute input value of Pins SRP and SRN of 0.3V, two 100Ω resistors R36 and R37 should be connected in series to the sampling signal.

Figure 2-5 Sampling resistor Kelvin connection

In summary, how to ensure high measurement accuracy is the key when designing sampling resistors. The following three points should be noted: (1) The connection method should be Kelvin connection, as shown in Figure 2-5; (2) The resistor selection should be made so that its temperature drift is less than 50ppm to reduce the drift of the measurement current caused by temperature changes; (3) Design a suitable filter circuit to reduce noise interference, see Section 3.1 for details.

3. Fuel gauge

3.1 Coulomb meter interface

In order to improve the accuracy of the sampling current, in addition to processing the sampling resistor, the interface circuit of the input signal can also be designed. As shown in Figure 3-1, a low-pass filter circuit is designed for the sampling signal to reduce signal noise.

Figure 3-1 Coulomb counter interface low-pass filter circuit

Pins SRP and SRN are connected with 0.1μF filter capacitors C13 and C14 to filter out noise in the frequency range of 100k-100MHz. The two 100pF and 0.1μF capacitors in the middle are used to filter out noise above 100MHz. All the above filter components should be placed as close to the input as possible, and the path from the signal at both ends of the sampling resistor to the filter circuit should be kept parallel. Finally, laying a ground plane around the filter circuit will help to achieve a better filtering effect, as shown in Figure 3-2.

Figure 3-2 Coulomb counter interface filter circuit layout

3.2 Power Management

The power supply system of BQ40z80 consists of three parts: BAT from the battery, VCC from the charger, and PBI for internal instantaneous power supply. The power supply is managed according to different working states, as shown in Figure 3-3.

Figure 3-3 BQ40z80 power supply management system

Usually, the primary power supply of the device is provided by the battery, which is introduced from the positive electrode through an input Schottky diode to Pin BAT. The input range is 2.2-32V. The diode can quickly isolate the device from the battery in the case of a transient voltage drop caused by a short circuit. It is determined by the maximum voltage of the battery used. For example, a 40V Schottky diode is selected for a 24V battery. Pin VCC is the second-level power input of the device, connected to the common drain of the FETs of CHG and DSG. When the battery is in a low power state, if there is a charger on the PACK, the device will use the energy of the charger as the power supply when it detects that the voltage of BAT is lower than VCC. Finally, the third-level power supply comes from Pin PBI, which is used as an instantaneous energy backup for transient power failure. This pin is connected to the ground through a 2.2μF capacitor, and its instantaneous energy source is the energy stored on the capacitor.

3.3 System Detection

System detection means that BQ40z80 detects whether PACK has a charger or load connected through Pin PRES*, which is usually connected to ground. The device provides a 4μs pulse per second on the pin through a current source with a typical value of 10-20μA. In order to make the test pulse value lower than the VIL limit, a resistor of 20kΩ or less should be connected in series, as shown in Figure 3-4.

Figure 3-4 System detection circuit

At the same time, since the system detection signal is connected to PACK, in order to protect the device during external electrostatic discharge, the Pin PRES* of BQ40z80 has integrated ESD protection. Only a 1kΩ resistor needs to be connected to achieve 8 kV ESD protection.

3.4 Internal voltage balance

BQ40z80 contains an internal integrated voltage balancing module that can simultaneously achieve a maximum 10mA balancing current for each battery cell to achieve voltage balancing.

As shown in Figure 3-5, taking two cells as an example, when BQ40z80 determines that the voltage of one or more cells is abnormal through voltage sampling at the input end, it will drive the internal bypass FETs to turn on, forming a loop at both ends of the single cell. The bypass current formed consumes the abnormal voltage at both ends of the cell in the form of heat through the resistance on the loop. Therefore, the total resistance on the loop determines the size of the bypass current, that is, the strength of voltage balancing.

Figure 3-5 Internal integrated voltage balancing module

The resistor consists of two parts. The first is the on-resistance Rds(on)=200Ω of the bypass FETs, and the second is the RC filter circuit at the cell voltage input. Therefore, the total bypass resistance of each cell is 2×100+200 = 400Ω. If the typical value of a cell voltage is 4V, the bypass current is about 10mA. It should be noted that the voltage balancing process is not a process in which the bypass FETs are fully turned on until the balancing is completed, but the bypass FETs are turned on at a certain duty cycle every hour. For BQ40z80, its typical value is 75%, which can be modified by software. At this time, for a battery with a capacity of 2000mAh and an abnormal SOC of 10%, the time required to balance with a duty cycle D is t =2000mAh×10%/(10mA×D).

3.5 External voltage equalization module

BQ40Z80 contains an internal integrated voltage balancing module, which can achieve a maximum 10mA balancing current for each cell at the same time to achieve voltage balancing. If a faster voltage balancing capability is required, an external voltage balancing module needs to be designed, as shown in Figure 3-6.

The external N-MOSFETs are equipped with low gate-source drive threshold voltage Vgs(th). Considering the conduction stability of FETs, the original 100Ω resistor in the input RC filter circuit is changed to 1kΩ. The working principle is as follows: When BQ40z80 controls the internal bypass FETs to turn on, an internal bypass loop is formed, and the two 1kΩ resistors and the on-resistance Rds(on)=200Ω of the FETs form a resistor divider with a voltage divider ratio of 0.454. Considering that the typical voltage range of a battery cell is 3-4.2V, when the voltage of a single battery cell is balanced, a voltage signal of 1.362-1.907V will be generated on the resistor through voltage division. This signal is the gate-source drive voltage of the external FETs, so the N-MOSFETs are turned on, the external bypass loop is opened, and the bypass current will be determined by the resistor on the external loop, which can be set by the user according to the needs.

Figure 3-6 External voltage balancing module

It should be noted that the principle of selecting the external bypass MOSFET is to make it have as low Vgs(th) as possible while considering the circuit voltage divider ratio to achieve successful and reliable driving, such as DMN2004DWK, NTZD3154N and Si1024X. For more details, please refer to the application document, Fast Cell Balancing Using

External MOSFET (SLUA420).

3.6 Temperature

BQ40z80 provides up to 4 temperature input signals TS1, TS2, TS3 and TS4, which can be used for temperature detection of batteries, FETs, etc., and the object type and mode of detection can be configured by software. Pins TS1, TS2, TS3 and TS4 are integrated with a typical value of 18kΩ pull-up resistor, which can support 10kΩ NTC thermistor at 25℃ (PTC is not supported yet). It should be noted that lead-type thermistors are often used for battery temperature detection, which is convenient for fitting the battery surface and achieving better monitoring effect on battery temperature.

4 Applications for high current applications

In some special applications, such as electric vehicles, airplanes, etc., higher discharge current is usually required. Therefore, the following provides some solutions on how to design the circuit of BQ40z80 for high current applications for reference.

4.1 FETs and sampling resistor parallel connection scheme

The key point of designing for high current discharge is how to expand the current-bearing capacity of the main current loop, including the charge and discharge FETs and current sampling resistors on the loop. When FETs are required to pass a large current, considering the heat dissipation pressure and the rated current of the MOS, it is recommended to use a parallel MOS solution. When selecting, the limitation of the driving capability should be considered first and the switch tube with the smallest possible Qg should be selected. At the same time, the heat dissipation and loss pressure under the condition of large current conduction should be taken into account and the switch tube with the smallest possible Rds(on) should be selected. However, additional considerations are required for the current sharing problem that is easy to occur in parallel MOS, such as making the driving signal position as parallel as possible during layout.

For current sampling resistors, BQ40z80 itself supports parallel solutions. When selecting, the appropriate resistance value should be selected in combination with the required current value and the input voltage range of Pins SRP and SRN. At the same time, for heat dissipation considerations, it is recommended to leave a certain margin for the selection of rated power and package. For example, to achieve the sampling of 100A current, select two 1mΩ, 3W rated power, 2512 package resistors. However, for the sake of current sampling accuracy, it is crucial to ensure reliable Kelvin connection in the parallel solution.

4.2 Parallel drive capability solution

Obviously, the biggest problem with the parallel MOS solution is that the IC driving capability is limited. The maximum output load capacity of the BQ40z80's Pins CHG and DSG is about 10μA. You can refer to this value and the MOS's input capacitance, on-resistance, etc. to measure its driving capability. There are two solutions to this problem:

First, within the range of BQ40z80's Pins CHG and DSG capabilities, select a MOSFET with a Qg value that can be successfully driven and Rds(on) that meets the heat dissipation requirements. However, it should be noted that, generally speaking, these two values have an inverse relationship and need to be weighed. In addition, the MOS turn-on time will be correspondingly longer at this time. For example, if CSD18510Q5B is selected, Qg=118nC, Rds(on)=0.79mΩ (Vgs=10V), when used in parallel with 3, the turn-on time is about 14ms.

Second, when the MOS drive requirements exceed the driving capability of BQ40z80 or there are higher requirements for the turn-on time, the following two methods can be used to enhance the circuit driving capability through the design of external devices:

(1) Add an additional transistor to the output of Pins CHG and DSG to enhance its driving capability, as shown in Figure 4-1. However, an additional DC-DC with an output value higher than Vbat by about 10V is required to complete the power supply of the transistor. The pull-up resistor value should also be designed according to the MOS driving current requirements.

Figure 4-1 BQ40z80 and transistor drive circuit

(2) Add a high-side N-channel FET driver BQ76200 (BQ76200) to enhance its driving capability. As shown in Figure 4-2, this design will avoid the need for additional DCDC. The output signals of Pins CHG and DSG of BQ40z80 no longer directly drive MOS, but serve as the enable input of BQ76200, which is used to drive MOS, thereby solving the problem of insufficient driving capability.

Figure 4-2 BQ40z80 and BQ76200 drive circuit

When choosing this design, it should be noted that the output levels of Pins CHG and DSG of BQ40z80 are based on Vbat and PACK+ respectively, while the enable input of BQ76200 is based on VSS. The voltage levels between the two do not match, so level conversion is required. For the high level of the BQ9006 drive output, a resistor divider R1 and R2 are needed to transform the output voltage of BQ40z80 to make it consistent with the enable input range of BQ76200. At the same time, for the low level of BQ006 output, a P-FET is required to ensure that only when the output of Pin CHG is higher than Vbat, the P-FET is turned on, and BQ76200 will obtain the enable input through the resistor divider to avoid mis-conduction. The principle of selecting P-FET is that its Vgs(th) is about 10V, corresponding to the drive output of Pin CHG.

Secondly, attention should be paid to the selection of the resistor value of the voltage divider. Considering that the output current capability limit of Pin CHG is about 10μA and the output voltage is about Vbat+10V, the total resistance of R1 and R2 should limit the current within its capability. At the same time, the influence of a pull-down resistor with a typical value of about 1MΩ contained in the enable input Pin CHG_EN of BQ76200 on the voltage divider value should also be considered.

On the basis of realizing level conversion, the circuit of BQ76200 in parallel scheme needs to be further designed. First of all, in addition to supporting the series connection of charge and discharge FETs, BQ76200 also supports charging and discharging into two separate circuits, that is, the connection mode of charge and discharge FETs in parallel. When the current levels of discharge and charging in the application are quite different, it is possible to consider designing the charging and discharging circuits separately. Such a design can effectively reduce the number of charging FETs. After determining which connection mode to use, the capacitance value on Pin VDDCP should be calculated according to the specific situation of the FETs used. For more details, please refer to the technical application manual FET Configurations for the bq76200 High-Side N-Channel FET Driver (SLVA729A).

5 Reference Circuit Diagram

Author: Weng Iris