STM32 clock tree notes

1 STM32 has five clock sources: HSI, HSE, LSI, LSE, PLL
1.1  HSI: high-speed internal clock, RC oscillator, frequency is 8MHz, clock accuracy is poor, can be used as a backup clock source (clock safety system CSS).
1.2  HSE: high-speed external clock, can connect external crystal/ceramic resonator (4MHz~16MHz) or external clock source (HSE bypass, Max 25MHz).
1.3  LSI: low-speed internal clock, RC oscillator, frequency is 40kHz, large-capacity MCU can perform LSI clock calibration.
1.4  LSE: low-speed external clock, connect external crystal/ceramic resonator with a frequency of 32.768kHz.
1.5  PLL: phase-locked loop multiplier output, clock input source can select HSI/2, HSE or HSE/2. The multiplier can be selected from 2 to 16 times, with a maximum output of 72MHz.

Users can configure the frequency of the AHB bus, high-speed APB2 bus and low-speed APB1 bus through multiple prescalers. The maximum frequency of the AHB and APB2 domains is 72MHZ. The maximum allowed frequency of the APB1 domain is 36MHZ. The clock frequency of the SDIO interface is fixed to HCLK/2.
   The 40kHz LSI is used by the independent watchdog IWDG, and it can also be selected as the clock source of the real-time clock RTC. In addition, the clock source of the real-time clock RTC can also select LSE, or 128 division of HSE. The clock source of RTC is selected by RTCSEL[1:0].
   There is a full-speed USB module in STM32, and its serial interface engine requires a clock source with a frequency of 48MHz. This clock source can only be obtained from the PLL output, and can be selected as 1.5 division or 1 division, that is, when the USB module needs to be used, the PLL must be enabled and the clock frequency is configured to 48MHz or 72MHz.
   In addition, STM32 can also select a PLL output divided by 2, HSI, HSE, or system clock output to the MCO pin (PA8)
   The system clock SYSCLK is the clock source for most components in STM32. The system clock can be selected as PLL output, HSI or HSE. Before selecting the clock source, be sure to determine whether the target clock source has stable oscillation. Max=72MHz, it is divided into 2 channels, 1 channel is sent to I2S2CLK and I2S3CLK used by I2S2 and I2S3; the other channel is divided by the AHB divider (1/2/4/8/16/64/128/256/512) and sent to the following 8 modules:
① SDIOCLK clock for SDIO.
② FSMCCLK clock for FSMC.
③ HCLK clock for AHB bus, core, memory and DMA.
④ System timer clock (SysTick) sent to Cortex after being divided by 8.
⑤ Directly sent to the Cortex idle running clock FCLK.
⑥ Sent to the APB1 divider. The APB1 divider can select 1, 2, 4, 8, 16 frequency divisions, one of its outputs is used by the APB1 peripherals (PCLK1, maximum frequency 36MHz), and the other is sent to the timer (Timer2-7) 2, 3, 4 frequency multipliers. The frequency multiplier can select 1 or 2 frequency multiplication, and the clock output is used by timers 2, 3, 4, 5, 6, 7.
⑦ Sent to the APB2 divider. The APB2 divider can select 1, 2, 4, 8, 16 frequency divisions, one of its outputs is used by the APB2 peripherals (PCLK2, maximum frequency 72MHz), and the other is sent to the timer (Timer1, Timer8) 1, 2 frequency multipliers. The frequency multiplier can select 1 or 2 frequency multiplication, and the clock output is used by timer 1 and timer 8. In addition, the APB2 divider has an output for the ADC divider. After the frequency division, the ADCCLK clock is sent to the ADC module. The ADC divider can be selected as 2, 4, 6, or 8 divisions.
⑧ After the frequency division, it is sent to the SDIO AHB interface for use (HCLK/2) 2

Clock  output enable control
Many of the above clock outputs have enable controls, such as the AHB bus clock, core clock, various APB1 peripherals, APB2 peripherals, etc.
   When a module needs to be used, the corresponding clock must be enabled first.
   It should be noted that the timer multiplier, when the APB division is 1, its multiplier value is 1, otherwise its multiplier value is 2.
   The devices connected to APB1 (low-speed peripherals) are: power interface, backup interface, CAN, USB, I2C1, I2C2, UART2, UART3, SPI2, window watchdog, Timer2, Timer3, Timer4. Note that although the USB module requires a separate 48MHz clock signal, it should not be the clock for the USB module to work, but only the clock provided to the serial interface engine (SIE). The clock for the USB module to work should be provided by APB1.
   The devices connected to APB2 (high-speed peripherals) are: GPIO_A-E, USART1, ADC1, ADC2, ADC3, TIM1, TIM8, SPI1, ALL


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The following figure is a block diagram of the STM32F10xx clock system. Through this figure, you can see at a glance the path of the clock generation of each component, and you can also easily calculate the clock frequency of each part. The

four clock sources of STM32 (HSI, HSE, LSI and LSE) are also marked in the figure; the clock monitoring system (CSS) in the middle of the figure is a safety setting that appears in many ST7 microcontrollers.

Special attention: On the right side of the figure, there is a multiplier before the output timer clock. Its operation is not controlled by the program, but is automatically selected by the hardware according to the output of the APB pre-divider of the previous level. When the division factor of the APB pre-divider is 1, this multiplier has no effect; when the division factor of the APB pre-divider is greater than 1, this multiplier performs a frequency doubling operation, that is, multiplying the frequency output by the APB pre-divider by 2, which can ensure that the timer can get the highest 72MHz clock pulse.