Key points of AVR M16 ADC application design

Under normal circumstances, the ADC successive approximation conversion circuit requires a sampling clock between 50kHz and 200kHz to achieve maximum accuracy. When the conversion accuracy is required to be less than 10 bits, the ADC sampling clock can be higher than 200kHz to obtain a higher sampling rate.

The ADC module contains an ADC clock source with a prescaler, which can divide the system clock greater than 100KHz to obtain a suitable ADC clock for ADC use. The prescaler's division coefficient is set by the ADPS bit in the ADCSRA register. Once the ADEN bit in the ADCSRA register is set to "1" (ADC starts working), the prescaler starts counting. When the ADEN bit is "1", the prescaler will always work; when the ADEN bit is "0", the prescaler is always in reset state.

The time it takes for the AVR ADC to complete a conversion is shown in Table 6.2.5. As can be seen from the table, it usually takes 13-14 ADC clocks to complete an ADC conversion. It takes 25 ADC clocks from the start of the ADC to the completion of the first conversion, because the analog circuit part of the ADC unit needs to be initialized.

When the ADSC bit in the ADCSRA register is set and the ADC conversion is started, the A/D conversion will start at the rising edge of the subsequent ADC clock. When a normal A/D conversion starts, a sampling and holding time of 1.5 ADC clock cycles is required (a sampling and holding time of 13.5 ADC clock cycles is required after the ADC is first started). When an A/D conversion is completed, the conversion result is written to the ADC data register, and ADIF (ADC interrupt flag) will be set. In single conversion mode, ADSC is also cleared at the same time. The user program can set the ADSC bit again, and a new conversion will start at the next rising edge of the ADC clock.

When the ADC is set to automatic trigger mode, the rising edge of the trigger signal will start an ADC conversion. The result of the conversion will be kept until the next rising edge of the trigger signal appears, and then a new ADC conversion will start. This ensures that the ADC performs a conversion at a certain time interval. In this mode, the ADC requires a sampling and holding time of 2 ADC clock cycles.

In free continuous conversion mode, a new conversion starts immediately after one conversion is completed. At this time, the ADSC bit remains at "1".

2. Selection of ADC input channel and reference power supply

The MUXn and REFS1, REFS0 bits in the ADMUX register are actually a buffer that is connected to a temporary register that the MCU can read randomly. This structure ensures that the ADC input channel and reference power supply can only be changed at a safe point in the ADC conversion process. Before the ADC conversion starts, the channel and reference power supply can be continuously updated. Once the conversion starts, the channel and reference power supply will be locked and kept for enough time to ensure the normal ADC conversion. In the last ADC clock cycle before the conversion is completed (when the ADIF position of ADCSRA is "1"), the channel and reference power supply begin to be updated again.

Note: Since A/D conversion starts on the rising edge of the first ADC clock after setting ADSC, do not write a new channel or reference power supply to the ADMUX register within one ADC clock cycle after setting ADSC.

Be careful when changing the differential input channel. Once the differential input channel is determined, the gain amplifier needs 125µs to stabilize. Therefore, do not start the A/D conversion within 125µs after selecting the new differential input channel, or discard the conversion results during this period. After changing the reference power supply by changing REFS1 and REFS0 in ADMUX, the first differential conversion should also follow the above time processing process.

1) When changing the ADC input channel, the following should be followed to ensure that the correct channel is selected:

    In single conversion mode, always change the channel setting before starting the conversion. Although the input channel change occurs within 1 ADC clock cycle after the ADSC bit is written to "1", it is easiest to wait until the conversion is completed before changing the channel selection.

In continuous conversion mode, always change the channel settings before starting the ADC to start the first conversion. Although the input channel change occurs within 1 ADC clock cycle after the ADSC bit is written to "1", the simplest method is to wait until the first conversion is completed before changing the channel settings. However, since a new conversion has been automatically started at this time, the current conversion result still reflects the conversion value of the previous channel, and the next conversion result will be the value of the newly set channel.

2) ADC voltage reference source

The reference voltage (VREF) of the ADC determines the range of the A/D conversion. If the input voltage of the single-ended channel exceeds VREF, the conversion result will be close to 0x3FF (1023). The reference voltage VREF of the ADC can be selected as AVCC or the internal 2.56V reference source of the chip, or as the reference voltage source externally connected to the AREF pin.

    AVCC is connected to the ADC through a passive switch. The internal 2.56V reference source is generated by the internal bandgap reference source (VBC) through an internal amplifier. Note that no matter what internal reference power supply is selected, the external AREF pin is directly connected to the ADC. Therefore, a capacitor can be connected between the AREF pin and ground to make the internal reference power supply more stable and noise-resistant. The voltage value of the reference power supply VREF can be obtained by measuring the AREF pin with a high-impedance voltmeter. Since VREF is a high-impedance source, only capacitive loads can be connected to this pin.

If an external fixed voltage source is connected to the AREF pin, any internal reference power supply cannot be used, otherwise the external voltage source will be short-circuited. The external reference power supply range should be between 2.0V and AVCC-0.2V. The first ADC conversion result after the reference power supply is changed may not be accurate, and it is recommended to discard the conversion result.

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3. ADC conversion results

After the A/D conversion is completed (ADIF = 1), the conversion result can be obtained in the ADC data register (ADCL and ADCH). For the A/D conversion of single-ended input, the conversion result is:

ADC = (VIN × 1024) / VREF

Where VIN represents the voltage on the selected input pin, VREF represents the voltage of the selected reference power supply. 0x000 means the voltage of the input pin is the analog ground, and 0x3FF means the voltage of the input pin is the reference voltage value minus one LSB.

For a differential conversion, this results in:

ADC=(VPOS-VNEG)×GAIN×512/VREF

For example, if the differential input channel is selected as ADC3-ADC2, with a gain of 10, a reference voltage of 2.56V, and left-end alignment (ADMUX=0xED), the voltage on the ADC3 pin is 300mV, and the voltage on the ADC2 pin is 500mV.

Then ADCR=（300-500）×10×512/2560=-400=0x270, ADCL=0x00, ADCH=0x9C.

If the result is right-aligned (ADLAR="0"), ADCL=0x70, ADCH=0x02.

Appendix 2: In-depth discussion of ADC application design

Although the AVR has a 10-bit ADC integrated inside, in actual applications, to truly achieve a 10-bit accurate and relatively stable ADC is not as simple as the example in the previous section. It requires further comprehensive and detailed consideration from the aspects of hardware and software. The following are some key points that should be considered in ADC design and application.

1. Stability of AVcc.

AVcc is the power supply for ADC. If AVcc is unstable, it will affect the conversion accuracy of ADC. In Figure 10-5, the system power supply is connected to AVcc after passing through an LC filter. This can effectively suppress the high-frequency noise in the system power supply and improve the stability of AVcc. In addition, when using ADC in situations with higher requirements, try not to use the ports on the PA port that are not used as ADC input as digital I/O ports. Because the working power supply of the PA port is provided by AVcc, if there is a relatively large current fluctuation on the PA port, it will also affect the stability of AVcc.

2. Selection and determination of reference voltage VREF

In practical applications, the correct reference voltage VREF should be selected according to the range of the input measurement voltage in order to obtain better conversion accuracy. The reference voltage VREF of the ADC also determines the range of A/D conversion. If the input voltage of the single-ended channel exceeds VREF, the conversion results will all be close to 0x3FF. Therefore, the reference voltage of the ADC should be slightly larger than the highest value of the analog input voltage.

The reference voltage VREF of ADC can be selected as AVCC, or the 2.56V reference source inside the chip, or the reference voltage source externally connected to the AREF pin. The external reference voltage should be stable and greater than 2.0V (when the working voltage of the chip is 1.8V, the external reference voltage should be greater than 1.0V). In situations with higher requirements, it is recommended to connect a standard reference voltage source to the AREF pin as the reference power supply for the ADC.

3. ADC channel bandwidth and input impedance

Regardless of whether single-ended input conversion or differential input conversion is used, the input voltage of all analog input ports should be between AVcc and GND.

In single-ended ADC conversion mode, the input frequency bandwidth of the ADC channel depends on the ADC conversion clock frequency. A conventional ADC conversion requires 13 ADC clocks. When the ADC conversion clock is 1MHz, the number of ADC sampling conversions in one second is about 77K. According to the sampling theorem, the bandwidth of the ADC channel is 38.5KHz.

The bandwidth of the differential ADC conversion is determined by the bandwidth of the differential amplifier inside the chip, which is 4KHz.

    The typical value of AVR ADC input impedance is 100MΩ. To ensure accurate measurement, the output impedance of the measured signal source should be as low as possible, which should be below 10K.

4. Selection of ADC sampling clock

Under normal conditions, the AVR ADC successive comparison circuit needs a sampling clock of 50K~200KHz to achieve the maximum conversion accuracy. A normal ADC conversion process requires 13 sampling clocks. Assuming that the ADC sampling clock is 200KHz, the highest sampling rate is 200K/13=15.384K. Therefore, according to the sampling theorem, the theoretical maximum frequency of the measured analog signal is 7.7K!

Although the ADC sampling clock can be set to 1M, it does not improve the ADC conversion accuracy, but reduces the conversion accuracy (limited by the successive comparison hardware circuit), so the AVR ADC cannot complete the task of high-speed ADC. If the required conversion accuracy is less than 10 bits, the sampling clock can be higher than 200KHz to achieve a higher sampling frequency.

The ADC sampling clock is selected as follows: given or estimated the highest frequency fs of the analog signal to be measured, the sampling frequency is 4-10 times of fs, and then multiplied by 13 to get the ADC sampling clock frequency, which should be between 50K and 200KHz. If the frequency is greater than 200KHz, the 10-bit accuracy of the ADC cannot be guaranteed. If the frequency is less than 50Khz, a value between 50K and 200KHz can be selected.

5. Suppression of analog noise

The digital circuits outside and inside the device will generate electromagnetic interference and affect the accuracy of analog measurements. If the ADC conversion accuracy is very high, the following techniques can be used to reduce the impact of noise:

(1) Make the analog signal path as short as possible. Analog signal lines should pass through the analog ground wiring board and be kept as far away from high-speed switching digital signal lines as possible.

(2) The AVcc pin of the AVR should be connected to the digital power supply Vcc through an LC network.

(3) Use the ADC noise suppressor function to reduce the noise from inside the MCU.

(4) If some ADC pins are used as general digital output ports, do not change the status of these pins during the ADC conversion process.

6. ADC Calibration

Due to objective reasons such as the nonlinearity of the amplifier in the ADC part of the AVR, the ADC conversion result will have errors. If you want to obtain high-precision ADC conversion, you also need to correct the ADC result. For specific methods, please refer to the AVR application note AVR120 (avr_app_120.pdf). This application design reference introduces the types of errors and correction solutions in detail.

7. Improvement of ADC accuracy

With the above mentioned points guaranteed, the accuracy of ADC can be improved appropriately through software means, such as taking average of multiple measurements, software filtering algorithm, etc. AVR application note AVR121 (avr_app_121.pdf) introduces a software implementation using oversampling algorithm, which can improve the accuracy of ADC to 11 bits or higher, of course, this is achieved on the basis of spending more time.