AVR MCU fuse settings

(1) In the AVR device manual, the fuse bit is defined as programmed (Programmed) and unprogrammed (Unprogrammed). "Unprogrammed" means the fuse state is "1" (disabled); "Programmed" means the fuse state is "0" (enabled). Therefore, the process of configuring the fuse bit is actually "configuring the fuse bit to be unprogrammed state "1" or programmed state "0"".

(2) When using programming tool software that allows you to determine the fuse bit status value by checking the box, please first read the software instructions carefully to understand whether "√" means setting the fuse bit status to "0" or "1".

(3) When using the programming download program in CVAVR, special attention should be paid. Since the initial state of most fuse bits is defined as "1" when the CVAVR programming download interface is initially opened, do not use the "all" option in its programming menu options. At this time, the "all" option will configure the fuse bits of the chip according to the initial state definition of the fuse bits, but in fact it is often not the configuration result required by the user. If you want to use the "all" option, you should first use "read->fuse bits" to read the actual state of the fuse bits in the chip, and then use the "all" option.

(4) Before using a new AVR chip, you should first check the configuration of its fuse bits, then configure the fuse bits according to actual needs, and record the status of each fuse bit for filing.

(5) After the AVR chip is encrypted, only the data in the internal Flash and E2PROM of the chip cannot be read. The status of the fuse bits can still be read, but the configuration cannot be modified. The chip erase command clears the data in the Flash and E2PROM, and at the same time configures the status of the two lock bits to "11", which is in an unlocked state. However, the chip erase command does not change the status of other fuse bits.

(6) The correct operation procedure is: when the chip is unlocked, download the running code and data, configure the relevant fuse bits, and finally configure the chip lock bits. After the chip is locked, if the fuse bits are found to be incorrectly configured, the chip erase command must be used to clear the data in the chip and unlock it. Then re-download the running code and data, modify the configuration-related fuse bits, and finally configure the chip lock bits again.

(7) When using ISP serial download programming, the SPIEN fuse bit should be configured to "0". The default state of the SPIEN bit when the chip leaves the factory is "0", indicating that ISP serial download data is allowed. Only when this bit is in the programmed state "0" can ISP download be performed through the SPI port of the AVR. If this bit is configured as unprogrammed "1", ISP serial download data is immediately prohibited. At this time, the SPIEN state can only be reset to "0" through parallel mode or JTAG programming to open ISP. Under normal circumstances, the SPIEN state should be kept at "0". Allowing ISP programming will not affect the I/O function of its pins, as long as the ISP interface and the devices connected in parallel are isolated when designing the hardware circuit, such as using series resistors or circuit breaker jumpers.

(8) When your system does not use the JTAG interface for download programming or real-time online simulation debugging, and the pins of the JTAG interface need to be used as I/O ports, the fuse bit JTAGEN must be set to "1". The JTAGEN state of the chip is "0" by default when it leaves the factory, indicating that the JTAG interface is allowed and the external pins of JTAG cannot be used as I/O ports. When the JTAGEN state is set to "1", the JTAG interface is immediately disabled. At this time, JTAG can only be reset to "0" and JTAG can only be opened through parallel mode or ISP programming.

(9) In general, do not set the fuse to define the RESET pin as I/O (such as setting the ATmega8 fuse RSTDISBL to "0"). This will cause the ISP download programming to be unable to proceed, because before entering the ISP mode programming, the RESET pin needs to be pulled low to put the chip into the reset state first.

(10) When using an AVR chip with an internal RC oscillator, pay special attention to the configuration of the fuse bit CKSEL. Generally, the default state of the CKSEL bit when the chip leaves the factory is to use the internal 1MHz RC oscillator as the system clock source. If you use an external oscillator as the system clock source, do not forget to correctly configure the CKSEL fuse bit first, otherwise the timing of your entire system will be problematic. When your design does not use an external oscillator (or a specific oscillation source) as the system clock source, do not misoperate or mistakenly configure the CKSEL fuse bit to use an external oscillator (or other different types of oscillation sources). Once this happens, the chip cannot be operated using the ISP programming method (because the ISP method requires the chip's system clock to work and generate timing control signals), and the chip looks "broken". At this time, the only way to save it is to remove the chip and use the parallel programming method, or use the JTAG method (if JTAG is allowed and there is a JTAG interface on the target board). Another way to solve the problem is to try to temporarily add different types of oscillation clock signals to the crystal pins of the chip. Once the ISP can operate the chip, immediately configure CKSEL to use the internal 1MHz RC oscillator as the system clock source, and then reconfigure CKSEL correctly according to the actual situation.

(11) When using an AVR chip that supports IAP, if you do not use the BOOTLOADER function, be careful not to set the fuse bit BOOTRST to "0", as it will cause the chip to not start executing the program from 0x0000 of the Flash when it is powered on. The default state of the BOOTRST bit is "1" when the chip leaves the factory. For the configuration of BOOTRST, the design of the BOOTLOADER program, and the application of IAP, please refer to the relevant content in this chapter.

2. mega8 fuse bit: 1: Not programmed (not selected) 0: Programmed (selected)
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Fuse bit  description  Default setting
******************************************
RSTDISBL:  Reset or I/O function selection  1  1: Reset function; 0: I/O function (PC6)
WDTON:  Watchdog switch  1  1: Watchdog on (enabled by WDTCR); 0: Watchdog disabled
SPIEN:  SPI download enabled  0  1: SPI download disabled; 0: SPI download enabled (Note: This item is not available when using SPI programming)
EEAVE:  EEPROM data retention during  programming 1  1: Not retained; 0: Retained
BODEN:  BOD function control  1  1: BOD function disabled; 0: BOD function enabled
BODLEVEL:  BOD level selection  1  1: 2.7V level; 0: 4.0V level
BOOTRST:  Reset entry selection  1  1: The program starts to execute from the address 0x0000; 0: The program starts to execute from the entry address determined by the boot area
******************************************
BOOTSZ1/0:  Boot program size and entry  00 
00: 1024Word/0xc00;
01: 512Word/0xe00;
10: 256Word/0xf00;
11: 128Word/0xf80
***************************************
BLB02/01:  Program area instruction bit selection  11
11: Both SPM and LPM instructions are allowed to execute
10: SPM instruction prohibits writing program area
01: Boot area LPM instruction prohibits reading program area content; if the interrupt vector is defined in the boot area, the interrupt is prohibited from executing in the program area.
00: SPM instruction prohibits writing program area; Boot area LPM instruction prohibits reading program area content; if the interrupt vector is defined in the boot area, the interrupt is prohibited from executing in the program area.
***************************************
BLB12/11:  Boot sector instruction bit selection  11
11: Both SPM and LPM instructions are allowed to execute
10: SPM instruction prohibits writing to the boot sector
01: Program area LPM instruction prohibits reading the boot sector content; if the interrupt vector is defined in the program area, the interrupt is prohibited from executing in the boot sector.
00: SPM instruction prohibits writing to the boot sector; program area LPM instruction prohibits reading the boot sector content; if the interrupt vector is defined in the program area, the interrupt is prohibited from executing in the boot sector.
***************************************
LB2/1:  Program area encryption bit selection  11 
11: Unencrypted
10: Program and EEPROM programming functions disabled, fuse bit locked
00: Program and EEPROM programming and verification functions disabled, fuse bit locked
(Note: program other fuse bits first, then program the encryption bit)
***************************************
CKSEL3/0:  Clock source selection  0001
CKOPT:  Crystal oscillator selection  1
SUT1/0:  Reset start time selection  10
***************************************
CKSEL3/0＝0000: External clock, CKOPT＝0: Allow the chip's internal XTAL1 pin to connect a 36PF capacitor to GND; CKOPT＝1: Disable the capacitor
----------------
CKSEL3/0＝0001-0100: Calibrated internal RC oscillator, CKOPT is always 1
0001: 1.0M
0010: 2.0M
0011: 4.0M
0100: 8.0M
----------------
CKSEL3/0=0101-1000: External RC oscillation, CKOPT=0: Allow the chip's internal XTAL1 pin to connect a 36PF capacitor to GND; CKOPT=1: Disable this capacitor
0101: <0.9M
0110: 0.9-3.0M
0111: 3.0-8.0M
1000: 8.0-12.0M
----------------
CKSEL3/0=1001: External low-frequency crystal oscillator, CKOPT=0: Allow the chip's internal XTAL1/XTAL2 pins to connect a 36PF capacitor to GND; CKOPT=1: Disable this capacitor
----------------
CKSEL3/0=1010-1111: External crystal oscillator, ceramic resonator, CKOPT=0: High amplitude oscillation output; CKOPT=1: Low amplitude oscillation output
101X: 0.4-0.9M
110X: 0.9-3.0M
111X: 3.0-8.0M
***************************************
SUT1/0:  Reset start time selection
When different crystal oscillators are selected, SUT is different.

3. Clock selection list
Clock source  start delay  fuse
External clock  6 CK + 0 ms  CKSEL="0000" SUT="00"
External clock  6 CK + 4.1 ms  CKSEL="0000" SUT="01"
External clock  6 CK + 65 ms  CKSEL="0000" SUT="10"
Internal RC oscillation 1MHZ  6 CK + 0 ms  CKSEL="0001" SUT="00"
Internal RC oscillation 1MHZ  6 CK + 4.1 ms  CKSEL="0001" SUT="01"
Internal RC oscillation 1MHZ  6 CK + 65 ms  CKSEL="0001" SUT="10"
Internal RC oscillation 2MHZ  6 CK + 0 ms  CKSEL="0010" SUT="00"
Internal RC oscillation 2MHZ  6 CK + 4.1 ms  CKSEL="0010" SUT="01"
Internal RC oscillator 2MHZ  6 CK + 65 ms  CKSEL="0010" SUT="10"
Internal RC oscillator 4MHZ  6 CK + 0 ms  CKSEL="0011" SUT="00"
Internal RC oscillator 4MHZ  6 CK + 4.1 ms  CKSEL="0011" SUT="01"
Internal RC oscillator 4MHZ  6 CK + 65 ms  CKSEL="0011" SUT="10"
Internal RC oscillator 8MHZ  6 CK + 0 ms  CKSEL="0100" SUT="00"
Internal RC oscillator 8MHZ  6 CK + 4.1 ms  CKSEL="0100" SUT="01"
Internal RC oscillator 8MHZ  6 CK + 65 ms  CKSEL="0100" SUT="10"
External RC oscillation ≤ 0.9MHZ  18 CK + 0 ms  CKSEL="0101" SUT="00"
External RC oscillation ≤ 0.9MHZ  18 CK + 4.1 ms  CKSEL="0101" SUT="01"
External RC oscillation ≤ 0.9MHZ  18 CK + 65 ms  CKSEL="0101" SUT="10"
External RC oscillation ≤ 0.9MHZ  6 CK + 4.1 ms  CKSEL="0101" SUT="11"
External RC oscillation 0.9-3.0MHZ  18 CK + 0 ms  CKSEL="0110" SUT="00"
External RC oscillation 0.9-3.0MHZ  18 CK + 4.1 ms  CKSEL="0110" SUT="01"
External RC oscillation 0.9-3.0MHZ  18 CK + 65 ms  CKSEL="0110" SUT="10"
External RC oscillator 0.9-3.0MHZ  6 CK + 4.1 ms  CKSEL="0110" SUT="11"
External RC oscillator 3.0-8.0MHZ  18 CK + 0 ms  CKSEL="0111" SUT="00"
External RC oscillator 3.0-8.0MHZ  18 CK + 4.1 ms  CKSEL="0111" SUT="01"
External RC oscillator 3.0-8.0MHZ  18 CK + 65 ms  CKSEL="0111" SUT="10"
External RC oscillator 3.0-8.0MHZ  6 CK + 4.1 ms  CKSEL="0111" SUT="11"
External RC oscillator 8.0-12.0MHZ  18 CK + 0 ms  CKSEL="1000" SUT="00"
External RC oscillator 8.0-12. 0MHZ 18 CK + 4.1 ms  CKSEL="1000" SUT="01"
External RC oscillator 8.0-12.0MHZ  18 CK + 65 ms  CKSEL="1000" SUT="10"
External RC oscillator 8.0-12.0MHZ  6 CK + 4.1 ms  CKSEL="1000" SUT="11"
Low frequency crystal oscillator (32.768KHZ)  1K CK + 4.1 ms  CKSEL="1001" SUT="00"
Low frequency crystal oscillator (32.768KHZ)  1K CK + 65 ms  CKSEL="1001" SUT="01"
Low frequency crystal (32.768KHZ)  32K CK + 65 ms  CKSEL="1001" SUT="10"
Low frequency quartz/ceramic oscillator (0.4-0.9M) 258 CK + 4.1 ms  CKSEL="1010" SUT="00"
Low quartz/ceramic oscillator (0.4-0.9M)  258 CK + 65 ms  CKSEL="1010" SUT="01"
Low quartz/ceramic oscillator (0.4-0.9M)  1K CK + 0 ms  CKSEL="1010" SUT="10"
Low quartz/ceramic oscillator (0.4-0.9M)  1K CK + 4.1 ms  CKSEL="1010" SUT="11"
Low quartz/ceramic oscillator (0.4-0.9M)  1K CK + 65 ms  CKSEL="1011" SUT="00"
Low Quartz/Ceramic Oscillator (0.4-0.9M)  16K CK + 0 ms  CKSEL="1011" SUT="01"
Low Quartz/Ceramic Oscillator (0.4-0.9M)  16K CK + 4.1ms  CKSEL="1011" SUT="10"
Low Quartz/Ceramic Oscillator (0.4-0.9M)  16K CK + 65ms  CKSEL="1011" SUT="11"
Medium Quartz/Ceramic Oscillator (0.9-3.0M)  258 CK + 4.1 ms  CKSEL="1100" SUT="00"
Medium Quartz/Ceramic Oscillator (0.9-3.0M)  258 CK + 65 ms  CKSEL="1100" SUT="01"
Quartz/Ceramic Oscillator (0.9-3.0M)  1K  CK + 0 ms  CKSEL="1100" SUT="10" Quartz /Ceramic Oscillator (0.9-3.0M  ) 1K CK + 4.1 ms  CKSEL="1100" SUT="11" Quartz/Ceramic Oscillator (0.9-3.0M)  1K CK + 65 ms  CKSEL="1101" SUT="00" Quartz/Ceramic Oscillator (0.9-3.0M) 16K CK + 0 ms  CKSEL="1101" SUT="01" Quartz/Ceramic Oscillator (0.9-3.0M) 16K CK + 4.1ms  CKSEL="1101" SUT="10" Quartz/Ceramic Oscillator ( 0.9-3.0M  )  16K CK + 65ms  CKSEL="1101" SUT="11" High Quartz/Ceramic Oscillator (3.0-8.0M)  258 CK + 4.1 ms  CKSEL="1110" SUT="00" High Quartz/Ceramic Oscillator (3.0-8.0M)  258 CK + 65 ms  CKSEL="1110" SUT="01" High Quartz/Ceramic Oscillator (3.0-8.0M)  1K CK + 0 ms  CKSEL="1110" SUT="10" High Quartz/Ceramic Oscillator (3.0-8.0M)  1K CK + 4.1 ms  CKSEL="1110" SUT="11" High Quartz/Ceramic Oscillator (3.0-8.0M)  1K CK + 65 ms  CKSEL="1111" SUT="00" High quartz/ceramic oscillator (3.0-8.0M)  16K CK + 0 ms  CKSEL="1111" SUT="01" High quartz/ceramic oscillator (3.0-8.0M)  16K CK + 4.1ms  CKSEL="1111" SUT="10" High quartz/ceramic oscillator (3.0-8.0M)  16K CK + 65ms  CKSEL="1111" SUT="11" Note: 1. Factory default settings Note: When CKOPT=1 (unprogrammed), the maximum operating frequency is 8MHZ internal RC oscillation 1MHZ  6 CK + 4.1 ms  CKSEL="0001" SUT="01"