8-bit resolution ADC inside Songhan MCU

;Purpose: To learn the internal 8-bit resolution ADC and data processing
;Full code download: http://www.51hei.com/f/shrad.rar
 CHIP SN8F27E65
//{{SONIX_CODE_OPTION
 .Code_Option WDT_CLK Flosc/4
 .Code_Option Reset_Pin P04
 .Code_Option LVD LVD_Max ; 3.3V Reset
 .Code_Option Watch_Dog Disable ;Turn off watchdog
 .Code_Option Low_Fcpu Flosc/1
 .Code_Option High_Clk IHRC_16M ; Internal 16M RC Oscillator
 .Code_Option High_Fcpu Fhosc/1
 .Code_Option Security Enable
 .Code_Option Noise_Filter Enable
//}}SONIX_CODE_OPTION
 
 
 DATAC EQU P4M
 DATA EQU P4
 LEDC EQU P0M
 LED EQU P0

.DATA; data
 ORG 0
 TEMP DS 1
 ACCBUF DS 1
 PflagBUF DS 1

.CODE;Program code
 ORG 0000H
 JMP A0
 ORG 000BH
 JMP T0
 ORG 0015H
A0: B0BCLR FT0IEN;Turn off T0 interrupt
 B0BCLR FT0ENB;Disable T0 interrupt
 MOV A,#16;Set T0 clock
 B0MOV T0M,A;
 MOV A,#16;Load initial value
 B0MOV T0C,A;
 B0BCLR FT0IRQ;Clear interrupt flag
 B0BSET FT0IEN;Turn on T0 interrupt
 B0BSET FT0ENB;Enable T0 interrupt
 B0BSET FGIE;Turn on general interrupt
 MOV A,#3;Display value
 MOV 41H,A
 
 MOV A,#2;Display value
 MOV 42H,A
 MOV A,#1;Display value
 MOV 43H,A
 MOV A,#0;Display value
 MOV 44H,A
;****************************************************
;Display settings
;************************************************
A1: MOV A,#11111110B ;Display bit code
 MOV 31H,A
 MOV A,#4;Display bit number
 MOV 33H,A
 B0MOV H,#0 ; Clear "H" to address RAM bank 0.
 B0MOV L,#41H ; Set register address.
 
A2:
 CLR ADM; Clear ADC mode register ADM
 
 CLR ADR; Clear ADR register
 
 MOV A,#00000001B
 B0MOV P5CON,A; Select P5.0 as ADC input channel
 
 MOV A,#00000000B
 B0MOV P5M,A; Set P5 port to input mode
 
 MOV A,#00000000B
 B0MOV P5UR,A; Disable P5 port to pull-up mode
 
 B0BSET FADENB; Enable ADC
 CALL M005; Delay
 MOV A,#00001000B
 OR ADM,A; Set ADCHS[3:0] to select ADC input channel
 
 B0BSET FGCHS; Enable ADC input channel
 
 B0BSET FADS; Start AD conversion.
A3:
 B0BTS1 FEOC; Determine whether the conversion is completed
 JMP A3
;****************************
; MOV A,ADB
 MOV A,#0
 MOV 60H,A
 MOV A,ADB; In 8-bit mode, the converted data is stored in ADB
 MOV 61H,A
;****************************
 CALL CL1; Call data processing
 MOV A,64H; Display the processed data
 MOV 44H,A; Thousands
 MOV A,63H
 MOV 43H,A; Hundreds
 
 MOV A,62H
 MOV 42H,A; Tens
 
 MOV A,61H
 MOV 41H,A; Units

 B0BCLR FEOC; clear flag
 CALL M008; delay
 
 JMP A2
 
; ***************************************************
; T0 interrupt
; **************************************************
T0: B0BCLR FT0IEN; turn off T0 interrupt
 B0BCLR FT0ENB; disable T0 interrupt
 B0XCH A,ACCBUF; push stack
 B0MOV A,PFLAG;
 B0MOV PFLAGBUF,A;
 MOV A,#0FFH; clear display
 B0MOV DATAC,A;
 B0MOV DATA,A;
 MOV A,#0FFH;
 B0MOV LEDC,A;
 MOV A,#0FFH;
 B0MOV LED,A;
T1:
 MOV A,#0FFH; set as output port
 B0MOV DATAC,A;
 B0MOV Y,#Q1$M; encoding table address
 B0MOV Z,#Q1$L; encoding table address
 B0MOV A, @HL; indirect addressing
 ADD Z, A; find the code to be displayed
 MOVC; check the table, the upper eight bits exist R, the lower eight bits exist ACC
 B0MOV DATA, A; data output
 
 
 MOV A, #0FFH; set to output port
 B0MOV LEDC, A

 MOV A,31H;Bit code
 B0MOV LED,A
 MOV A,31H;To process the bit code, since there is no RL but only RLC, now process C here
 MOV 32H,A
 RLC 32H
 RLCM 31H;Move bit code
 INCMS L;Display data control register processing
 CALL M001;Delay to increase brightness
 MOV A,#0FFH;Clear display
 B0MOV DATAC,A
 B0MOV DATA,A
 MOV A,#0FFH
 B0MOV LEDC,A
 MOV A,#0FFH
 B0MOV LED,A
 DECMS 33H;Automatically subtract 1 to determine whether it is also displayed. Complete
 JMP T1[page]
 
 MOV A,#11111110B ;Display bit code
 MOV 31H,A
 MOV A,#4;Display bit number
 MOV 33H,A
 B0MOV H,#0 ; Clear "H" to address RAM bank 0.
 B0MOV L,#41H; Set register address.
 B0MOV A,PFLAGBUF; Pop stack
 B0MOV PFLAG,A;
 B0XCH A,ACCBUF;
 MOV A,#16; Set T0 clock
 B0MOV T0M,A;
 MOV A,#16; Reload initial value
 B0MOV T0C,A;
 B0BCLR FT0IRQ; Clear interrupt flag
 B0BSET FT0IEN; Enable interrupt
 B0BSET FT0ENB; Enable interrupt
 B0BSET FGIE; Enable general interrupt
 RETI;

CL1:
;******************************
; MOV A,#60H
; MOV 62H,A
;
; MOV A,# 11111111b
;MOV 61H,A
 
 

;****************************
 CALL CL2
 MOV A,65H
 AND A,#11110000B
 MOV 60H,A
 SWAP 60H
 MOV 62H,A; Tens digit
 MOV A,65H
 AND A,#00001111B
 MOV 61H,A; Units digit
 MOV A,63H; Ten thousand digit
 MOV 65H,A
 
 MOV A,64H
 AND A,#00001111B
 MOV 63H,A; Hundreds digit
 MOV A,64H
 AND A,#11110000B
 MOV 64H,A
 SWAPM 64H;Thousand digit
 RET
 
 
CL2: MOV A,#0
 MOV 63H,A
 MOV 64H,A
 MOV 65H,A
 MOV A,#16
 MOV 67H,A
CL3: B0BCLR FC
 RLCM 61H; (low 8 bits)
 RLCM 60H; (high 8 bits)
 MOV A,65H; tens digit
 ADC A,65H;
 DAA;
 MOV 65H,A;
 MOV A,64H; hundreds digit
 ADC A,64H;
 DAA;
 MOV 64H,A;
 MOV A,63H; 10,000-bit
 ADC A,63H;
 DAA;
 MOV 63H,A;
 
 DECMS 67H;
 JMP CL3;
 RET;
 
 
 
 
 
 
 
;***************** *************************
;Delay subroutine
;******************* ***********************
M001: MOV A,#1
 MOV 51H,A
M002: MOV A,#24
 MOV 52H,A
M003: MOV A, #250
 MOV 53H,A
M004: DECMS 53H
 JMP M004
 DECMS 52H
 JMP M003
 DECMS 51H
 JMP M002
 RET

M005: MOV A,#200
 MOV 55H,A
M006: DECMS 55H
 JMP M006 
 RET
M007: MOV A,#1
 MOV 56H,A
M008: MOV A,#20
 MOV 57H,A
M009: MOV A,#250
 MOV 58H,A
M010: DECMS 58H
 JMP M010
 DECMS 57H
 JMP M009
 DECMS 56H
 JMP M008
 RET
 
 
 
;**********************************************
;Coding table
;******************************************
Q1: DW 00C0H ;0
      DW 00F9H ;1
      DW 00A4H ;2
      DW 00B0H ;3
      DW 0099H ;4
      DW 0092H ;5
      DW 0082H ;6
      DW 00F8H ;7
      DW 0080H ;8
      DW 0090H ;9
      DW 0088H ;A
      DW 0083H ;B
      DW 00C6H ;C
      DW 00A1H ;D
      DW 0086H ;E
      DW 008EH ;F
      endp