STM32 SPI Notes

        I thought SPI was very simple, so I used it directly without looking at it carefully. This time, when I was debugging a chip, a strange problem occurred. I thought it was a problem with the program logic, and I wasted several days without finding the cause. Today, I obediently checked some manuals and finally found a clue in the "STM32 Incomplete Manual". Now I simply summarize SPI. First, let me talk about the problems I encountered recently.

        Problem 1: I mistakenly thought that reading SPI data by directly reading the SPIx->DR register can be completed.
        I have never paid attention to this problem, and I am very ashamed. It turns out that the SPI clock is only generated when writing data to the DR register, and it will not be generated when reading (I have not confirmed it from any information yet, but I guess it is like this). So to read the data sent by the slave, the master must first send a "DUMMY" data. The content of this data is not important. The purpose is just to generate a set of clocks for the slave, and the slave's data is sent out along this set of clocks.
        The process of master reading and writing data to slave is as follows:
        Write: master writes data to DR, generates clock, and data is shifted from MOSI pin to slave's MOSI pin;
        Read: master writes DUMMy to DR, generates clock, and DUMMy is sent from MOSI to slave (this data is meaningless), and the read data is shifted from slave's MISO pin to master's MISO pin.

        Question 2: When configured as two-wire full-duplex, as mentioned above, when the master writes data, the SPI of stm32 also reads data into the master's DR register (although both reading and writing are DR, they are actually two different registers). Ignoring this point is the cause of this problem.
       Before I read data from the acquisition chip, I need to send a read data instruction to the chip. After sending the instruction, theoretically, the acquisition chip will automatically wait for the data to be sent. As long as I send a DUMMy to generate a set of clocks on the stm32 side, I can read data from DR. However, when sending the read instruction, STM32 also reads useless data into DR. Before the data is taken away, it will not accept new data. Therefore, when DUMMY is sent later, the read register DR is not updated, so the data read is naturally wrong.
        The solution is to read the data once and clear DR after sending the instruction to receive the next data.


        The following is a summary of other key points of SPI.
Pin definition:
        MISO: Master input/slave output
        MOSI: Master output/slave input
        SCK: Serial port clock, as the output of the master device and the input of the slave device
        NSS: Slave select

        For NSS, for the slave device, inputting a low level indicates the selection of the slave device. This signal is provided by the NSS pin in hardware NSS mode; in software NSS mode, it is controlled by the internal SSI bit, and the NSS pin can be used as a normal IO.
        For the master device, if the NSS output is enabled, NSS will output a low level and can be connected to the NSS of the slave device. When the slave device is in hardware NSS mode, it will automatically become a slave SPI device (multi-master environment is not allowed). If the NSS output is turned off: operation in a multi-master environment is allowed.