Cortex-M0 processor

The ARM Cortex-M0 processor is the smallest ARM processor currently available. The chip area of ​​this processor is very small, the energy consumption is extremely low, and the code required for programming is very small, which allows developers to directly skip the 16-bit system and obtain the performance of a 32-bit system at a cost close to that of an 8-bit system. The ultra-low gate count of the Cortex-M0 processor allows it to be used in analog and mixed analog and digital devices.

 

Why choose Cortex-M0? The advantages of

the smallest ARM processor,

the Cortex-M0, in code density and power efficiency mean that it is a logical and cost-effective upgrade for 8/16-bit systems in a wide range of applications, while retaining tool and binary upward compatibility with the more powerful Cortex-M3 and Cortex-M4 processors. For applications that require lower power or more design options, the fully compatible Cortex-M0+ processor is an ideal candidate. The

low-power

Cortex-M0 processor consumes only 16µW/MHz (90LP process, minimum configuration) at less than 12K gates, thanks to the processor's expertise as a leader in low-power technology and a major driver of ultra-low-power devices. [page]

Simple

With only 56 instructions, you can quickly master the entire Cortex-M0 instruction set and its C-friendly architecture, making development simple and fast. The choice of fully deterministic instruction and interrupt timing makes it easy to calculate response times. 

Optimized connectivity

Enables low-energy network connected devices such as Bluetooth Low Energy (BLE), IEEE 802.15 and Z-wave, especially analog devices that require enhanced digital capabilities to pre-process and transmit data efficiently.

ARM Cortex-M0 Specification[td]        

ARM Cortex-M0 Features
ISA support	Thumb® / Thumb-2 subset
pipeline	3 Stages
Performance efficiency	1.62 CoreMark/MHz - 0.84 DMIPS/MHz (RVCT 5.0.90 compiler)
Interrupt	Non-maskable interrupt (NMI) + 1 to 32 physical interrupts
Sleep Mode	Integrated WFI and WFE instructions and "sleep on exit" functionality.             Sleep and deep sleep signals             Optional retention modes available with the ARM Power Management Toolkit
Bit Operations	The Cortex-M System Design Toolkit can be used to implement the bit segment area
Enhanced instructions	Hardware single-cycle (32x32) multiplication option
debug	Optional JTAG and Serial Wire Debug ports. Up to 4 breakpoints and 2 watchpoints

    

ARM Cortex-M0 implementation data*
	180ULL             (7 rail, typically 1.8v, 25C)	90LP             (7-track, typically 1.2v, 25C)	40G             (9 rails, typically 0.9v, 25C)
Dynamic Power Consumption	73µW/MHz	16µW/MHz	4µW/MHz
Plan area	0.13 mm2	0.04 mm2	>0.01 mm2

* Base available configuration includes 1 IRQ + NMI, debug not includedARM

Cortex-M Technology

Each Cortex-M series processor has specific advantages: adopting some basic technologies, which make Cortex-M processors suitable for a wide range of embedded applications.

RISC Processor Core	Thumb-2® Technology
High performance 32-bit CPU Deterministic operations Compact and low-latency pipeline	Optimal mix of 16/32-bit instructions 30% smaller code size than 8-bit devices No negative impact on performance
Low Power Mode	Nested Vectored Interrupt Controller (NVIC)
Integrated sleep state support Multiple power domains Architecture-based software control	Low latency, low jitter interrupt response No assembly programming required   Interrupt service routines written in pure C language
Tools and RTOS Support	CoreSight Debug and Trace
Extensive third-party tool support Cortex Microcontroller Software Interface Standard (CMSIS) Maximize software reuse	JTAG or 2-pin Serial Wire Debug (SWD) connection   Support for multiple processors

CMSIS

The ARM Cortex Microcontroller Software Interface Standard (CMSIS) is a vendor-neutral hardware abstraction layer for the Cortex-M processor family. CMSIS enables consistent and simple processor software interfaces for interfacing peripherals, real-time operating systems, and middleware, simplifying software reuse. CMSIS reduces the learning curve for new microcontroller developers, thereby reducing time to market for new products.
In-depth: Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral part of the Cortex-M processor, providing the processor with superior interrupt handling capabilities.

The Cortex-M processor uses a vector table that contains the address of the function to be executed for a specific interrupt handler. When an interrupt is accepted, the processor pulls the address from this vector table.

To reduce gate count and increase system flexibility, the Cortex-M processor uses a stack-based exception model. Once an exception occurs, the Cortex-M processor pushes key general purpose registers onto the stack. Once the stack push and instruction fetch are complete, the interrupt service routine or fault handler is executed, and then the registers are automatically restored to resume normal execution of the interrupted program. This approach greatly facilitates application development by eliminating the need to write assembler wrappers that are required to perform stack operations for traditional C language interrupt service routines. The NVIC supports nesting (stacking) of multiple interrupts, allowing an interrupt to execute earlier by applying higher priority. Comprehensive response to hardware interrupts

The interrupt response of the Cortex-M series processors is the number of cycles from the issuance of the interrupt signal to the execution of the interrupt service routine. It includes: 

    Detection of interrupts
    Optimal handling of back-to-back or late arriving (see below)
    Extraction of the interrupt vector address Stacking
    of fragile registers
    Jumping to the interrupt handler

These tasks are performed in hardware and are included in the interrupt response cycle time reported for the Cortex-M processor. In many other architectures, these tasks must be performed in the interrupt handler in software, introducing delays and complexity. [page]

Tail chaining in the NVIC

 
Back to back interrupt timing diagram

In the case of a back to back interrupt, conventional systems repeat the full state save and restore cycle twice, resulting in higher latency. Cortex-M processors simplify switching between active and pending interrupts by implementing Tail chaining technology in NVIC hardware. The processor state is automatically saved on entry to an interrupt and restored on exit from an interrupt. This significantly improves performance in low-frequency systems due to the reduced number of cycles compared to software implementations.

NVIC response to a late-arriving higher priority interrupt

 
Late interrupt arrival timing diagram

If a higher priority interrupt arrives late while a stack push is being performed for the previous interrupt, the NVIC immediately fetches a new vector address to service the pending interrupt as shown above. The Cortex-M NVIC provides a deterministic response to these possibilities and supports late arrivals and preemption.

Stack pop preemption by NVIC

 
Preemption timing diagram

Similarly, if an exception arrives, the NVIC will forgo the stack pop and immediately service the new interrupt as shown above. By preempting and switching to the second interrupt without completing the state restore and save, the NVIC achieves reduced latency in a deterministic manner.

Migrating from 8/16-bit to ARM Cortex-M

ARM Cortex-M Code Size Advantage Description

ARM Cortex-M processors offer superior code density over 8-bit and 16-bit architectures. This has great advantages in reducing memory requirements and maximizing the use of precious on-chip flash memory. We will analyze the reasons for this advantage in this section.

Instruction Width

Many people believe that 8-bit microcontrollers use 8-bit instructions, while microcontrollers based on ARM Cortex-M processors use 32-bit instructions, which is actually a misconception. In fact, for example, PIC18 and PIC16 instruction sizes are 16 and 14 bits respectively. For the 8051 architecture, while some instructions are 1 byte in length, many other instructions are 2 or 3 bytes in length. The same is true for 16-bit architectures, where some instructions may occupy 6 bytes or more of memory.

ARM Cortex-M processors feature ARM Thumb®-2 technology which provides excellent code density. With Thumb-2 technology, Cortex-M processors support the basic 16-bit Thumb instructions, which are extended to include more powerful 32-bit instructions. In many cases, the C compiler will use the 16-bit version of the instruction unless the operation can be performed more efficiently using the 32-bit version.

Instruction efficiency

This picture is incomplete without also taking into account the more powerful ARM Cortex-M processor instructions. In many cases, a single Thumb instruction can be equivalent to several 8/16-bit microcontroller instructions; this means that Cortex-M devices have less code and can therefore complete the same task at a lower bus speed.

Comparing 16-bit multiplication operations between processor architectures

8-bit Example		16-bit Example	ARM Cortex-M
MOV A, XL; 2-byte MOV B, YL; 3-byte MUL AB; 1-byte MOV R0, A; 1-byte MOV R1, B; 3-byte MOV A, XL; 2-byte MOV B, YH; 3-byte MUL AB; 1-byte ADD A, R1; 1-byte MOV R1, A; 1-byte MOV A, B; 2-byte ADDC A, #0; 2-byte MOV R2, A; 1-byte MOV A, XH; 2-byte MOV B, YL; 3-byte	MUL AB; 1-byte ADD A, R1; 1-byte MOV R1, A; 1-byte MOV A, B; 2-byte ADDC A, R2; 1-byte MOV R2, A; 1-byte MOV A, XH; 2-byte MOV B, YH; 3-byte MUL AB; 1-byte ADD A, R2; 1-byte MOV R2, A; 1-byte MOV A, B; 2-byte ADDC A, #0; 2-byte MOV R3, A; 1-byte	MOV R4,&0130h MOV R5,&0138h MOV SumLo,R6 MOV SumHi,R7 (operands are moved to or from the memory-mapped hardware multiply unit)	MULS r0,r1,r0

Note: Cortex-M multiplications actually perform 32-bit multiplications, and here we assume that r0 and r1 contain 16-bit data.

Compressed Data Footprint

It is important to note that the Cortex-M processor supports 8-bit and 16-bit data transfers, making efficient use of data memory. This means that programmers can continue to use the same data types they use in 8/16-bit targeted software.

Energy Efficiency Advantages

The demand for increasingly connected (e.g., USB, Bluetooth, and IEEE 802.15), with complex analog sensors (e.g., accelerometers and touchscreens), and with decreasing cost, has led to a need to more tightly integrate analog devices with digital functions to pre-process and transfer data. Most 8-bit devices do not provide the performance to support these tasks without a significant increase in MHz (and therefore power), so embedded developers need to look for alternative devices with more advanced processor technology. 16-bit devices have been used to address energy efficiency issues in microcontroller applications in the past. However, the relatively low performance of 16-bit devices means that they typically require longer active duty cycles or higher clock frequencies to complete the same tasks as 32-bit devices.

Makes software development easier

Software development for microcontrollers based on ARM Cortex processors can be much easier than for 8-bit microcontroller products. Not only are Cortex processors fully programmable in C, but they also come with a variety of advanced debugging features to help locate problems in the software. In addition to all the additional resources included in the MCU development kit, there are a large number of examples and tutorials on the Internet, many of which come from the websites of ARM processor-based MCU vendors.