Design of single chip microcomputer interrupt source system

Publisher:polkmmLatest update time:2015-03-23 Source: diangonKeywords:MCU Reading articles on mobile phones Scan QR code
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In the AT89S52 microcontroller, there are only two external interrupt request input terminals INT0 and INT1. In actual application systems, there are often more than two external interrupt sources, so the external interrupt sources must be expanded. The main methods are: expansion with timer/counter T0, T1; expansion by combining interrupt and query; expansion with serial port interrupt; expansion with priority encoder, etc. Here we focus on the first two methods.

1. Use timer/counter as interrupt source
   The two timer/counters T0 and T1 of AT89S52 microcontroller can work in counting mode. The initial count value is generally set to full scale (i.e. the maximum technical value of the timer). When a negative jump occurs on their counting input pins P3.4 or P3.5, the T0 or T1 counter will add 1 and generate an overflow interrupt. With this feature, P3.4 and P3.5 can be used as external interrupt request input lines, and the overflow interrupt of the counter is used as an external interrupt request flag.
Set T0 to mode 2 (automatically load constants) external counting mode, the time constant is 0FFH, interrupts are allowed, and the CPU opens interrupts. Its initialization program is:
ORG 0000H; jump to the initialization program
MOV TMOD, #06H; T0 is mode 2, counter mode
MOV TL0, #0FFH; the initial count value is full scale
MOV TH0, #0FFH; the initial count value is full scale
SETB TR0; set TR0 to 1, start T0
MOV IE, #82H; set interrupt enable, EA bit in IE is 1, ET0 bit is 1
   When the external interrupt request input line connected to the P3.4 pin has a negative jump, TL0 plus 1 overflows, TF0 is set to 1, and an interrupt request is sent to the CPU. At the same time, the content of TH0 is automatically sent to TL0, so that TL0 restores the initial value of 0FFH. In this way, each negative jump on the P3.4 pin sets TF0 to 1, sends an interrupt request to the CPU, and when the CPU responds to the interrupt request, the program counter PC goes to 000BH to execute the external interrupt service program. At this time, P3.4 is equivalent to the edge-triggered external interrupt source input line. Similarly, the P3.5 pin can also be treated similarly.
2. The method of combining interrupts with inquiries The
  method of combining interrupts with inquiries is to sort the multiple external interrupt sources in the system according to their importance, connect the highest-level interrupt source to an external interrupt source input terminal of MCS-51 (for example, to a pin), and connect the remaining interrupt sources to another external interrupt input terminal () by the wire "OR" method, and connect them to an I/O port at the same time, such as P1 port as shown in Figure 4-5. The interrupt request is generated by the hardware circuit, and the identification of the interrupt source is processed by program inquiries. The query order is determined by the priority of the interrupt source. The figure shows the connection circuit of five external interrupt sources, in which devices 1~4 are connected through OC gates and connected to P1.0~P1.3, all using level triggering. Device 0 is the highest-level interrupt source and is used as the input signal of external interrupt 0 alone. This method is relatively simple to expand, but when the number of external interrupt expansions is large, the query time is relatively long, resulting in low program execution efficiency.


Figure 1. System design with multiple external interrupt sources

The interrupt service routine of external interrupt 1 is as follows:
ORG 1000H
LJMP INTR
INTR: PUSH PSW; protect the context
PUSH A
JNB P1.0, IR1; P1.0 pin is 0, transfer to device 1 interrupt service routine
JNB P1.1, IR2; P1.1 pin is 0, transfer to device 2 interrupt service routine
JNB P1.2, IR3; P1.2 pin is 0, transfer to device 3 interrupt service routine
JNB P1.3, IR4; P1.3 pin is 0, transfer to device 4 interrupt service routine
INTR1: POP A; restore the context
POP PSW     
RETI; interrupt return

IR1: …… ; Device 1 interrupt service routine entry
AJMP INTR1 ; Jump to the instruction indicated by INTR1
IR2: …… ; Device 2 interrupt service routine entry
AJMP INTR1 ; Jump to INTR1
IR3: …… ; Device 3 interrupt service routine entry
AJMP INTR1 ; Jump to INTR1
IR4: …… ; Device 4 interrupt service routine entry
AJMP INTR1 ; Jump to INTR1

Keywords:MCU Reference address:Design of single chip microcomputer interrupt source system

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