; ; ; With the increasing application of I2C bus, there are more and more types of interface chips and memories compatible with I2C bus. Among them, digital potentiometers have been recognized by a large number of electronic engineering technicians for their convenient adjustment, long service life, little influence from physical environment, stable performance, etc., especially in the fields of audio products and control, which are increasingly valued by people. I2C bus digital potentiometer is a more representative one of the X9××× series digital potentiometers launched by Xicor Corporation of the United States. It is a monolithic CMOS microcircuit that integrates several E2POT non-volatile digital potentiometers. It has a two-wire serial I2C bus interface, is easy to control by software, can directly read and write the sliding end position, can be cascaded, and other advanced features. This article takes X9241 as an example.
2 Structural principles
; ; ; X9241 includes an I2C interface and four digital potentiometers. Each digital potentiometer consists of a resistor array and its corresponding sliding end count register WCR, four 8-bit data registers R0~R3, etc. Its pin configuration is shown in Figure 1. 2.1 Resistor Array ; ; ; Each resistor array consists of 63 discrete resistor segments connected in series. The physical terminals of each resistor array are equivalent to the fixed terminals (VH and VL input terminals) of the mechanical potentiometer. The VH and VL of each array and the contact point (i.e., tap) between each resistor segment are connected to the sliding output terminal VW through a FET switch; and the position of the sliding terminal VW in the resistor array is controlled by WCR. |
;
Figure 1 X9241 pin configuration diagram |
Among them, VW0, VW1, VW2 and VW3 are the sliding ends of the four potentiometers respectively; VL0, VL1, VL2 and VL3 are the low ends of the four potentiometers respectively; VH0, VH1, VH2 and VH3 are the high ends of the four potentiometers respectively; A0, A1, A2 and A3 are address lines (used to set the lower 4 bits of the slave address); SDA and SCL are serial data and serial clock respectively; VCC and VSS are power supply and ground respectively |
; ; ; If two, three or four of the four resistor arrays are connected in series, a digital potentiometer with 127, 190 or 253 taps can be formed.
; ; ; ; The resistance types of the X9241 potentiometer resistor array vary depending on the suffix. When Y, W, and U are respectively, the resistor array is four 2kΩ, four 10kΩ, and four 50kΩ digital potentiometers; and when M is, the resistance values of the four internal digital potentiometers are 2kΩ, 10kΩ, 10kΩ, and 50kΩ respectively.
2.2 Slider Count Register WCR
; ; ; The sliding end count register WCR is actually a 6-bit counter with a decoded output, which is used to select the position of the FET switch of 64-choose-one, that is, to control the position of the sliding end in the resistor array. WCR is a volatile memory, and its content can be rewritten by instructions. When power is on, the content of data register R0 is loaded (note: this value may be different from the value when power is off).
2.3 Data Register
; ; ; The contents of the data register can be read or written by the user, and its contents can be transferred to the sliding count register WCR to set the position of the sliding end. Each digital potentiometer has four 8-bit non-volatile data registers R0~R3.
2.4 Serial Interface
; ; ; X9241 supports the directional protocol of I2C serial bidirectional bus: in actual application, X9241 is a slave device, the host starts the data transmission and provides the clock for the sending and receiving operations. The relationship between the signals of data line SDA and clock line SCL (start condition, stop condition and response condition) is shown in Figure 2.
3 Device addressing and instruction structure
3.1 Device Addressing
; ; ; After the start, the master device outputs the address of the slave device it wants to access. The format of the address is as follows:
0 |
1 |
0 |
1 |
A3 |
A2 |
A1 |
A0 |
; ; ; For X9241, the upper 4 bits of this address are fixed to: 0101, and the lower 4 bits are determined by the state of the physical device address A0~A3 input terminals. In this way, X9241 compares the serial data stream with the state of the address input terminal. If all bits are compared successfully, the device makes a response on the bus.
3.2 Instruction Structure
; ; ; After the master device sends the start condition and device address, and the slave device responds, the next byte sent to X9241 includes the instruction and register pointer information. Its format is as follows:
I3 |
I2 |
I1 |
I0 |
P1 |
P0 |
R1 |
R0 |
; ; ; The first two bits (R0 and R1) of the lower 4 bits indicate one of the four registers, and the last two bits (P0 and P1) select which of the four potentiometers; the upper 4 bits determine the instruction. X9241 has a total of 9 instructions, see Table 1.
; ; ; Table 1 X9241 instructions
instruction |
I3 |
I2 |
I1 |
I0 |
P1 |
P0 |
R1 |
R0 |
Function Description |
Read WCR |
1 |
0 |
0 |
1 |
1/0 |
1/0 |
× |
× |
Read the contents of the sliding end count register specified by P1 and P0 |
Write WCR |
1 |
0 |
1 |
0 |
1/0 |
1/0 |
× |
× |
Write new values to the sliding end count registers specified by P1 and P0 |
Read Data Register |
1 |
0 |
1 |
1 |
1/0 |
1/0 |
1/0 |
1/0 |
Read the contents of the registers specified by P1, P0 and R1, R0 |
Write Data Register |
1 |
1 |
0 |
0 |
1/0 |
1/0 |
1/0 |
1/0 |
Write new values to the registers specified by P1, P0 and R1, R0 |
XFT Data Register to WCR |
1 |
1 |
0 |
1 |
1/0 |
1/0 |
1/0 |
1/0 |
Transfer the contents of the register specified by P1, P0 and R1, R0 to the WCR associated with it |
XFT WCR to Data Register |
1 |
1 |
1 |
0 |
1/0 |
1/0 |
1/0 |
1/0 |
Transfer the contents of WCR specified by P1 and P0 to the registers specified by R1 and R0 |
Global XFT Data
Register to WCR |
0 |
0 |
0 |
1 |
× |
× |
1/0 |
1/0 |
Transfer the contents of all four data registers specified by R1 and R0 to their corresponding WCRs |
Global XFT WCR to Data Register |
1 |
0 |
0 |
0 |
× |
× |
1/0 |
1/0 |
Transfer the contents of all WCRs to their corresponding data registers specified by R1 and R0 |
Increment / Decrement Wiper |
0 |
0 |
1 |
0 |
1/0 |
1/0 |
× |
× |
Enables increment/decrement of the contents of the wiper count register (WCR) specified by P1 and P0 |
; ; ; The 9 instructions include four two-byte instructions, four three-byte instructions and one increase/decrease instruction.
; ; ; (1) Two-byte instructions: These four two-byte instructions are used to exchange data between the WCR and one of the data registers; this transfer can occur between one of the four potentiometers and one of their auxiliary registers, or globally between all four potentiometers and one of their auxiliary registers; the operation timing is shown in Figure 2 (a). ;
; ; (2) Three-byte instructions: These four instructions are used to transfer data between the host and X9241, either between the host and a data register or between the host directly and the WCR; these instructions are to read and write the WCR (i.e. read and write the current position of the selected potentiometer's sliding end) or read and write the data register (i.e. read and write the contents of the selected non-volatile register); the operation timing is shown in Figure 2 (b).
; ; ; (3) Increase/decrease command: This command is different from other commands. Once this command is issued and X9241 has responded with an acknowledgment, the host can use the clock to trigger the selected sliding end to increase or decrease a resistance segment; the command timing of this operation is shown in Figure 2 (c). [page]
4 Series connection and control of potentiometers
; ; ; X9241 provides a mechanism to connect arrays in series, which can connect the sixty-three resistor elements of an array in series with the resistor elements of an adjacent array. The control bit is in the three-byte instruction. For the three-byte instruction, the data byte includes 6 bits (LSB) used to define the position of the sliding end plus the upper 2 bits: CM (serial case mode) and DW (disable wipe). The state of the CM bit is used to enable or disable the serial mode; when the CM bit of WCR is set to "0", the potentiometer is in normal working mode; when the CM bit is "1", it is connected in series with the adjacent high-numbered potentiometer. For example, if bit 7 of potentiometer WCR1 is set to "1", POT1 and POT2 are used in series. The state of the DW bit is used to enable or disable the sliding end. When the DW bit of WCR is set to "0" (or "1"), the sliding end is enabled (or disabled). When disabled, the sliding end is electrically isolated and floating. When working in series mode, the three output ends of the VH, VL and sliding end VW of the series array must be electrically connected to the outside. Except for one sliding end that is enabled, the rest of the sliding ends must be disabled. The user can change the position of the sliding end by changing the content of WCR.
5 Interface with GMS90/97 series microcontrollers
; ; ; Figure 3 is a representative connection between X9241 and GMS90/97 series single-chip microcomputer. The author has successfully used this connection method in audio systems and intelligent instruments as a gain feedback resistor, so that the gain of the amplifier can be adjusted by software programming within a wide range. In the actual application system design, the use of I2C bus digital potentiometers can reduce costs and simplify circuits; however, while digital potentiometers simplify hardware design, they increase the workload of software because access to them requires a set of strict and complex operations; if there is an interface program module, it is very convenient to use I2C bus digital potentiometers. For this reason, this article gives the interface program module between I2C bus digital potentiometers and GMS90/97 series single-chip microcomputers that the author has successfully applied, and readers can use it almost without modification; this program module can also be used for reading and writing serial E2PROMs with slight modifications. |
Figure 3 Typical connection between GMS90/97 series MCU and X9241 |
E2POT Driver Module
RW9241: | SCL | BIT | P1.4 |
SDA | BIT | P1.5 | |
INCDEC | BIT | 02H | |
; ;Increase or decrease position of the sliding end | |||
DEVICE | DATA | 50H |
; ;Device address |
COMMAND | EQU | 30H | |
; ; Command byte | |||
RD_DATA | EQU | 31H | |
; ;Read data |
WR_DATA | EQU | 32H | |
; ;Written data | |||
ACALL | START_IC | ||
; ;Set to start |
MOV | A, #DEVICE | ||
ACALL | WR_BYTE | ||
; ;Write device address | |||
MOV | A, COMMAND |
; ; According to the command and recognition word scattered transfer | |||
SWAP | A | ||
ANL | A,#0FH | ||
CJN | A,#09H,XRW1 |
; ; The high 4 bits of the instruction are 09H, indicating R_WCR |
AJMP | R_WCR | ||||
XRW1: | CJN | A,#0AH,XRW2 | |||
; ; The high 4 bits of the instruction are 0AH, indicating W_WCR | |||||
AJMP | W_WCR | ||||
XRW2: | CJN | A,#0BH,XRW3 | |||
; ; The high 4 bits of the instruction are 0BH, indicating R_ROM (read register) | |||||
AJMP | R_ROM | ||||
XRW3: | CJN | A,#0CH,XRW4 | |||
; ; The high 4 bits of the instruction are 0CH, indicating W_ROM (write register) | |||||
AJMP | W_ROM | ||||
XRW4: | CJN | A,#0DH,XRW5 | |||
; ; The high 4 bits of the instruction are 0DH, which means the value in the register is transferred to WCR | |||||
AJMP | ROM_WCR | ||||
XRW5: | CJN | A,#0EH,XRW6 |
; ; The high 4 bits of the instruction are 0EH, which means the value in WCR is transferred to the register | |||||
AJMP | WCR_ROM | ||||
XRW6: | CJN | A,#01H,XRW7 | |||
; ; The high 4 bits of the instruction are 01H, indicating that the value in the global register is transferred to WCR | |||||
AJMP | A_ROM_WCR | ||||
XRW7: | CJN | A,#08H,XRW8 | |||
; ; The high 4 bits of the instruction are 08H, indicating that the value in the global WCR is transferred to the register | |||||
AJMP | A_WCR_ROM | ||||
XRW8: | CJN | A,#02H,XRW9 | |||
; ; The high 4 bits of the instruction are 02H, indicating the specified WCR increase/decrease | |||||
AJMP | INC_DEC | ||||
XRW9: | ACALL | STOP_IC |
; ; Command execution completed, STOP and return |
RETI | ||||
R_WCR: | MOV | A, COMMAND |
; ;Read WCR subroutine | |||
ACALL | WR_BYTE | ||
ACALL | RD_BYTE | ||
MOV | RD_DATA, A | ||
ACALL | ACK_IC |
AJMP | XRW | ||
W_WCR: | MOV | A, COMMAND |
; ;Write WCR subroutine | |||||
ACALL | WR_BYTE | ||||
MOV | A, WR_DATA | ||||
ACALL | WR_BYTE | ||||
AJMP | XRW | ||||
R_ROM: | MOV | A, COMMAND |
; ;Read register subroutine | |||||
ACALL | WR_BYTE | ||||
ACALL | RD_BYTE | ||||
MOV | RD_DATA, A | ||||
ACALL | ACK_IC | ||||
AJMP | XRW | ||||
W_ROM: | MOV | A, COMMAND | |||
; ;Write register subroutine | |||||
ACALL | WR_BYTE | ||||
MOV | A, WR_DATA | ||||
ACALL | WR_BYTE | ||||
AJMP | XRW | ||||
ROM_WCR: | MOV | A, COMMAND | |||
; ;The data in the register is sent to the WCR subroutine | |||||
ACALL | WR_BYTE | ||||
AJMP | XRW | ||||
WCR_ROM: | MOV | A, COMMAND | |||
; ;WCR data send register subroutine | |||||
CALL | WR_BYTE | ||||
AJMP | XRW | ||||
A_ROM_WCR: | MOV | A, COMMAND | |||
; ;Data in global register is sent to WCR subroutine | |||||
ACALL | WR_BYTE | ||||
AJMP | XRW | ||||
A_WCR_ROM: | MOV | A, COMMAND | |||
; ;Subroutine to send data to register in global WCR | |||||
ACALL | WR_BYTE |
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