MSP430 Learning Bits - Watchdog Timer-EEWORLD

Collect

The watchdog has three working modes: stop mode, timer mode and watchdog mode.

The control register WDTCTL consists of two parts. The upper 8 bits are used as passwords, and the lower 8 bits are used to control the WDT. To control the WDT, the high-byte watchdog password must be written first. The password is 5AH. The WDTPW macro is generally defined as 5AH in the header file. The WDTCTL register bits are defined as follows:

15~8 7 6 5 4 3 2 1 0

Password HOLD NMIES NMI TMSEL CNTCL SSEL IS1 IS0

IS0 IS1 selects the timing output of the watchdog timer, where T is the input clock source period of WDTCNT. Generally, the macro defines WDTIS0 as 0x0001 and WDTIS1 as 0x0002.

0 T*2^15 (value after PUC reset)

1 T*2^13

2 T*2^9

3 T*2^6

SSEL selects the clock source of WDTCNT. Generally, the macro definition of WDTISSEL is 0x0004.

0 SMCLK (value after PUC reset)

1 ACLK

CNTCL When this bit is 1, clear WDTCTL. The general macro definition of WDTCNTL is 0x0008.

TMSEL working mode selection. Generally, the macro definition of WDTTMSEL is 0x0010.

0 Watchdog mode (default)

1 Timer mode

NMI selects the RST/NMI pin function and is reset after PUC. The general macro definition of WDTNMI is 0x0020.

0 RST/NMI pin is the reset pin

1 The RST/NMI pin is an edge-triggered non-maskable interrupt input.

NMIES selects the edge trigger mode of the interrupt. The general macro definition of WDTNMIES is 0x0040.

0 Rising edge triggers NMI interrupt

1 Falling edge triggers NMI interrupt

HOLD stops the watchdog timer to reduce power consumption. The general macro definition of WDTHOLD is 0x0080.

0 WDT function activated

1 Clock input is disabled and counting stops.

Therefore, the WDT can be set to work in watchdog mode, timer mode and low power mode according to the TMSEL and HOLD control bits in the WDTCTL register.

C language statement to implement low power mode:

WDTCTL = WDTPW + WDTHOLD;

C language statement to implement timer mode:

WDTCTL = WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0;

C language to implement the watchdog mode statement:

Set watchdog: WDTCTL = WDT_MRST_0_5 = WDTPW+WDTCNTCL+WDTIS1;

Clear watchdog: WDTCTL = WDTPW+WDTCNTCL; (default 32ms)

Keywords：MSP430 Reference address：MSP430 Learning Bits - Watchdog Timer

Previous article：MSP430 Learning Bits—IAR5.30
Next article：A picture to understand the low power mode of msp430f4371

Popular Resources
Popular amplifiers