LUCT low uncertainty clock tree design methods, algorithms and tools

What is LUCT?

Stratum 1 clock tree and Stratum 2 clock tree

Clock tree design and how it is designed are the main reasons for differences in system chip performance.

Historically, ASIC clock tree designers have used commercially available automated tools to design clock trees to ensure expected performance, such as execution time. However, this approach has not yielded satisfactory performance, such as clock skew and insertion delay. In addition, high complexity, frequency, and size designs have made traditional approaches completely unfeasible.

Low Uncertainty Clock Tree [LUCT] design and algorithms are concerned with the physical definition of the first-level clock tree implemented on a system-on-chip, enabling designers to overcome all the inefficiencies of traditional design approaches.

From the top-level root clock network (usually the PLL output) to the middle-level clock network, LUCT is a high-quality load-balanced clock tree, whose goal is to deliver the clock signal from the central phase-locked loop PLL to most areas of the chip. For details, see reference [1]. This document details the Low Uncertainty Clock Tree [LUCT] method and architecture, and summarizes the entire related design process from specification definition to cell layout and clock synthesis.

According to the definition in reference [2], this clock distribution method belongs to the structured clock tree. Reference [2] also summarizes the different existing clock design methods. From the clock source to the register, the entire clock tree consists of the first-level clock tree and the second-level (or local) clock tree. Commercial EDA tools need to implement the local clock tree.

LuctGenKit is a clock design tool developed by the Design Methodology Group of STMicroelectronics' Digital ASIC Product Division, which can complete the physical implementation process of the LUCT architecture.

Figure 1: Optimizing clock distribution in ASIC design

LUCT Tool Key Features
LuCT Clock Synthesis Tool provides all the important features of LuCT methodology:
o Balanced clock tree
- equal length and active load matching
- Obstacle awareness
- use low resistance high-level metal layers to transmit signals
- Shielding and parasitic matching
o Enhanced custom cell library to meet various signal strength requirements
o Support for multiple manufacturing processes, such as 32/28bulk, 28fdsoi, etc.
o Module layout, obstacle layout and obstacle avoidance
o Fully integrated with the layout and routing environment

LuCT Design Process

Figure 2: LuCTgenKit design process

The LuCTgenKit design flow consists of four phases, which are discussed in detail in the following sections of this article. The tool simplifies complex ASIC designs, especially in a design environment where multiple engineers are involved in the physical implementation of the entire project. In a typical design organization, the initial phase of physical implementation is database preparation and specification definition, and the final phase is mainly completed by dedicated LuCT engineers. Once database preparation and specification definition are completed, a single LuCT design engineer can complete the implementation and finalization of the entire top-level clock tree (which may be more than one clock tree) in one working day.

LuCT tool database preparation

Database preparation includes necessary design checks, layout planning rationality verification, reading power grid shape attributes and layout and routing tools. Among them, the layout and routing tools are used to connect special enhanced clock libraries and ensure the coherence of clock library layout through LuCT creation algorithms. This stage is also a key step to enable the structured clock tree to achieve the highest performance using existing technologies, especially in reducing voltage drop and crosstalk resistance.

LuCT tool LuCT specification definition

For each clock synthesis, the following information needs to be entered into the tool:
o Technology node
o Major clock tree starting point (PLL)
- X and Y coordinates
o Major clock tree endpoints
- X and Y coordinates on each leaf
o Frequency range
o Process-voltage-temperature corner
o Clock cell parameter selection
Designers can enter all the required data and design methods through a graphical user interface.
 

LuCT tool execution: Create LuCT

The Low Uncertainty Clock Tree Synthesis Automation Tool bundles the following:
- Design Specifications
- Floorplan Information (including Placement Barriers and Routing Barriers)
- Power Grid
- Design and Placement Rules
- Netlist
- Layout -
GUI
- Reports
- Finalization

Figure 3: LuCT application software graphical user interface menu

The LuCT tool generates the clock tree topology using an STMicroelectronics proprietary algorithm. The algorithm is based on balanced path lengths and equal-length homogeneous routing. The Lemon C++ graphics library [4] is required for chip floorplan modeling and initialization as well as path calculation. The clock tree creation process consists of the following steps:
o Grid generation: After reading the data from the floorplan, obstacle models and power grid shape models are generated. Starting from these models, a set of points (grid) representing the placement and routing spacing defined by the LuCT algorithm is calculated.
o Binary tree construction: Leaves are grouped into pairs using an STMicroelectronics proprietary algorithm. Each pair of leaves is merged by calculating equal-length paths containing obstacle avoidance points and a merge point (i.e., a point in the middle of the path). In this way, new leaves (merge points) are merged recursively until only one point (the root) remains, as shown in Figures 4 to 6.
o Clock driver and routing insertion: Clock driver insertion and routing optimization are performed in a bottom-up approach, considering obstacle placement and obstacle routing, respectively. [page]

Figure 4: Endpoint Collection

Figure 5: LuCT tree creation algorithm pairing decision and merging

Figure 6: Merge points generated at the previous level are paired and merged

Figure 7: Design flow using LuCT tool

Once the clock tree structure is generated, placement can be achieved using scripts within the place and route CAD tool. Custom rules are used to achieve placement configurations for high performance routing/tracing of multiple parallel clock drivers, via placement, and power noise aware placement.
The algorithm can be fine-tuned by modifying several parameters that have a significant impact on the binary tree architecture and creation.
Here are some examples of parameters:
o Leaf pair generation: can be automatic or manual
o Path distance calculation: can be pure Manhattan or barrier aware
o Kink minimization: choose the right attraction for routing nets
o Attract merging areas to move towards the center of the current stage by globally remapping the center at each routing/merging stage
o Clock tree performance metrics: barrier strength, clock skew/insertion delay performance vs barrier balance, clock congestion.

LuCT Tool Example and Results
Figure 8 shows the design of a clock tree for a 28FDSOI chip using LuCTgenKit according to the method discussed above. A 1GHz clock signal is distributed from the clock source to eight leaves, avoiding obstacles, balancing clock skew, and detecting obstacles. Figure 9 shows how equal-length calculations are performed when connecting high-level leaf pairs.

Figure 8

Figure 9

The main conclusion of this example is that the clock skew is very limited in terms of base delay, however, a large number of uncommon paths are present.