Design and Implementation of PowerPC Main Processor Board Based on CPCI Bus

0 Preface

The Compact PCI (CPCI) bus is an industrial computer bus standard launched by the "PCI Bus Industrial Computer Manufacturers Organization". It has been applied and developed most rapidly in recent years. It is developed from the general bus PCI on PCs. It has many advantages of the PCI bus, such as high bandwidth, high performance, plug-and-play, and low price, and the reliability of the passive backplane bus VME bus. The CPCI bus can reach a peak bandwidth of 132MB/s under the conditions of 33MHz clock and 32-bit data width, and a peak bandwidth of 528MB/s under the conditions of 66MHz clock and 64-bit data width.

PowerPC was designed by IBM, Apple and Motorola (whose semiconductor division is now spun off as Freescale) in 1993. PowerPC technology is based on RISC (Reduced Instruction Set Computer), which is derived from IBM's POWER (Performance Optimized Enhanced RISC) architecture. The PC in PowerPC stands for Performance Computing, and PowerPC is a super-powerful high-performance computing processor. Because PowerPC chips have the characteristics of high performance and low power consumption, they are mainly used in embedded systems.

1 System Structure

The system structure block diagram of the main processing board is shown in Figure 1. It mainly consists of four parts: power conversion function module, PowerPC function module, peripheral interface (RS232 serial port, Ethernet port and PMC expansion interface) function module, CPCI bus (PCI-to-PCI bridge) function module.

2 Hardware Design

2.1 Power conversion function module

Power supply design is very important in the entire hardware design. A good power supply design can ensure the normal and stable operation of the main processing board. There are 4 power supplies designed in the hardware: main power supply 5V (provided by the outside), PowerPC7410 core voltage 1.8V, bridge chip PC107 core voltage 2.5V, and each chip I/O voltage 3.3V.

The DC/DC switching power supply module of LINEAR Company is used to realize the voltage conversion of the main power supply from 5V to 1.8V, 2.5V and 3.3V, and the maximum output current of each channel is 10A. This DC/DC power supply module represents a new architecture for point-of-load power supply, which significantly simplifies the power supply design work. It has many excellent features: high power, high efficiency, small size, light weight, good heat dissipation performance, etc. In addition, it also has a unique performance of its clock-free current mode, which enables it to respond quickly to rapid changes in load current.

2.2 PowerPC Functional Module

2.2.1 Processor

The processor uses the PowerPC processor MPC7410 from Freescale. The main processor accesses the on-board resources through the bridge MPC107.

MPC7410 is a high-performance processor of the G4 series. G4 has greatly improved its performance based on G3, mainly in supporting symmetric multiprocessor (SMP) structure and introducing first-class Alti-Vec technology to handle vector operations. AltiVec technology is a 128-bit SIMD vector processing engine, which provides excellent processing performance for the fourth-generation PowerPC and improves its data processing capability by an order of magnitude.

The internal main frequency of MPC7410 is up to 500MHz, and each clock cycle can execute up to 8 instructions, including 4 vector operation (AltiVec) instructions and 2 integer instructions. By adding AltiVec technology, the processing capacity reaches 4G FLOPS. The low voltage operation of 1.8V greatly reduces the power consumption of the chip and facilitates heat dissipation, thereby greatly improving the stability of the system.

MPC7410 provides two bus modes: 60X bus mode and MPX bus mode. Different buses define different signals. The bus selection can be selected through the EMODE signal of MPC7410. When the EMODE signal is high when the HRESET signal becomes high, the 60X bus is selected. Conversely, when the EMODE signal is low when the HRESET signal becomes high, the MPX bus is selected. Since the 60X bus has excellent connection performance and high data transmission rate, the 60X bus is used as the connection between MPC7410 and the chipset in this design.

In addition, different core frequencies can be generated by setting the PLL signal of MPC7410. In this design, the external frequency of the processor is 100MHz, and a frequency coefficient of 5 is used, that is, the main frequency of the processor is 500MHz.

2.2.2 L2 Cache

The MPC7410 processor supports L2 Cache, and integrates an L2Cache interface controller inside, providing a bus timing control circuit for the L2 Cache interface. The cache memory can be accessed through the L2 Cache controller inside the processor. The main processing board implements a 2MByte L2 Cache with a data width of 72 bits, of which 8 bits are check bits and 64 bits are data bits.

2.2.3 Bridge

The bridge PC107 is a bridge chip/memory controller specially designed for PowerPC. It mainly realizes the bridge function from PowerPC to PCI, manages memory at the same time, and can run at a processor bus frequency of up to 133MHz. PC107 provides other functions necessary for embedded applications: processor bus interface, PCI bus interface, memory controller, intelligent input/output information controller, I2C controller, embedded programmable interrupt controller (EPIC), dual-channel integrated DMA controller, clock control part, etc. According to the different roles played in the circuit, the working mode of PC107 can be divided into host mode and agent mode. In the host mode, PC107 manages the memory and PCI bus part, and PowerPC is the main CPU of the whole system. In the agent mode, PC107 is used to communicate with the PCI host bridge, and PowerPC is a PCI device managed by the PCI host bridge. In this design, the working mode of PC107 is host mode.

2.2.4 Memory

The main processing board is designed with SDRAM memory, system FLASH memory, 64-bit user FLASH memory and NVSRAM memory. The capacity configuration is shown in Table 1.

2.2.4.1 SDRAM

In this design, SDRAM is used to store temporary data of the operating system and data and code of the application program, providing space for program operation and temporary file storage. The management of SDRAM is implemented by the memory controller. The bridge PC107 provides a high-speed SDRAM controller with a data width of 64 bits. The characteristics of the SDRAM interface of PC107: SDRAM devices must be compatible with the JEDEC specification of SDRAM, with optional data widths of 32 bits and 64 bits, support for paged access, support for 8 physical banks, and a maximum storage size of 1GB. The total capacity of SDRAM in this design is 512MB, and the bus clock is designed to be 100MHz. [page]

Due to the high frequency of the SDRAM clock bus, in order to improve the module's anti-interference ability and electromagnetic compatibility, strict requirements are put forward in PCB layout and wiring, including trace length, wiring path, impedance matching, line length, line width and spacing, and the signal integrity is analyzed through simulation in the early stage of PCB production to ensure the feasibility of the circuit.

2.2.4.2 FLASH

In this design, FLASH is divided into system FLASH and application FLASH. The system FLASH address is allocated at the high end of the storage space and is used for system startup. The BootRom boot program, power-on BIT test program, FLASH on-board programming program and operating system reside on the system FLASH. The capacity is 4MB, and the data width is 8 bits. The application FLASH is used to store application programs, with a total capacity of 256MB and a data width of 64 bits.

2.2.4.3 NVSRAM

NVRAM is a non-volatile memory used to store important system information, with a storage capacity of 32kB and an 8-bit data width.

2.2.5 Reset

There are two types of hardware resets for the main processing board: a. Power-on reset: When the external power supply 5V voltage is lower than 4.65V, the main processing board is in reset state. When the external power supply 5V voltage is higher than 4.65V, a reset of more than 200ms is generated, resetting the entire hardware and driving the CPCI bus reset signal at the same time; b. Manual reset input: caused by an external manual reset, resetting the entire hardware and driving the CPCI bus reset signal at the same time.

2.2.6 Watchdog

The main processing board has a watchdog function. When the watchdog function fails, a watchdog interrupt is generated. The default setting is disabled when powered on. The watchdog enable register is set inside the FPGA. The watchdog can be enabled or disabled by software. An interrupt is generated after the watchdog timer alarms. The watchdog timing period is set by hardware.

2.2.7 FPGA

FPGA is mainly responsible for the system reset, interrupt management and timing and logic control of related interfaces. This design uses Xilinx's Virtex series chips, which contain a wealth of registers/latches, synchronous and asynchronous set/reset signals, phase-locked loops, etc. This FPGA has 300,000 gates and 260 IO pins, which meets the design requirements. Another significant advantage of using FPGA is that the program can be continuously improved and real-time online programming can be performed.

2.2.8 Timer

PC107 provides 4 32-bit timers inside, the timing clock is 1/8 of the input clock of PC107, the accuracy is ±50ppm: the clock interrupt is input to the processor. Timer 1 is used as the timing clock of the operating system, and the other 3 timers are used as the application operation clock, which can be set by software, and the minimum timing period is 1ms.

2.3 Peripheral interface function module

2.3.1 Ethernet interface

The main processing board provides a 10MB/100MB adaptive Fast Ethernet interface. The design of this Ethernet interface is based on the PCI bus controlled by the bridge PC107. The basic block diagram is shown in Figure 2. It mainly consists of three parts: Ethernet controller, network isolation transformer and RJ45. The Ethernet controller uses Intel's highly integrated, high-performance, low-power 10/100Mbps Fast Ethernet control chip, which is dedicated to LAN-to-desktop solutions, such as the network access interface for servers, personal computers and mobile platforms, and complies with the LOM (LAN On Motherboard) design specification. The Ethernet controller communicates with the processor MPC7410 via the PCI bus through the on-chip command and status registers. It includes a MAC controller and a physical layer interface and can work in half-duplex mode and full-duplex mode.

The Ethernet controller drives the RJ45 network cable interface through a network isolation transformer to support 10/100BASE-T and achieve communication with the outside world.

2.3.2 RS232 serial port

The use of RS232 serial port makes this design more versatile and can communicate with devices with the same type of serial port. The main processing board provides two RS232 serial interfaces for communication with the development platform. The serial port part is implemented through EXAR's UART communication controller, which has a 16-byte FIFO and half-duplex control, and a maximum transmission rate of 1.5Mbps.

2.3.3 PMC expansion interface

The main processing board supports two 64bit/66MHz PMC expansion interfaces, which meet the PCI2.2 specification and can be expanded according to different system requirements, such as Gigabit network card, data acquisition card, graphics card, electronic disk, etc., making the system application more flexible.

2.4 CPCI bus function module

The main processing board is based on the CPCI bus, and the electrical characteristics of the CPCI bus are the same as those of the PCI bus. Currently, CPCI has replaced VME and STD industrial standards and become the new generation standard in the industry. The main processing board complies with the Eurocard industrial standard and defines a 6U (233.35mm×160mm) board size. The CPCI board connector has a total of 5 sockets, J1 to J5. The specification defines the signal line pins of J1 and J2, and J3 to J5 are custom sockets, as shown in Figure 3.

In this design, PLX's PCI-to-PCI bridge chip is used to implement the CPCI bus interface. This chip provides a standard 33MHz~66MHz PCI bus interface and supports 32-bit/64-bit PCI design. This chip does not require additional drive circuits and logic to connect PCI devices, and can be directly connected to the PCI signal inside the main processing board.

3. Underlying Software

The main processing board is transplanted with the robust VxWorks operating system, which provides support for many devices, and the device drivers are modularly designed with clear functions and standardized interfaces between modules.

The underlying software of the main processing board consists of two parts: BootRom boot code and VxWorks operating system image. When the system is powered on, the BootRom boot program is started first, and then the boot code segment and data segment are copied from Flash to SDRAM. After the boot code is executed, it jumps to the VxWorks image for execution. This system uses the network port to load the VxWorks image. This startup form has unique advantages, such as being able to adapt to hardware, convenient debugging and on-site upgrades, etc.

The BootRom boot code is solidified on the Flash of the main processing board. Its function is to start the minimum system of the main processing board to complete the purpose of loading and executing the VxWorks image. Compared with the VxWorks image, the BootRom has simpler functions and is easy to control in size. After the BootRom runs successfully, it starts the protection mode and file system support, drives auxiliary devices such as the network and serial port, eliminates the restrictions of the hardware environment on the program image, and makes the creation and loading of VxWorks applications free and arbitrary.

4 Conclusion

The CPCI bus is a high-speed synchronous shared bus. The main processing board based on this standard bus structure is designed with a high-performance RISC microprocessor MPC7410, and the VxWorks operating system is transplanted to ensure the stability and reliability of the main processing board based on the CPCI bus. In addition, the main processing board also provides a variety of standard interfaces, which can facilitate the system control, management and information exchange of other expansion boards in the system such as Ethernet cards, data acquisition cards, graphics cards, electronic disks, etc., and improve system performance. This main processing board has been applied to a certain model of display and control processor. It is also suitable for any CPCI bus system and can play a role in military or civilian signal processing fields such as sonar, radar, display and control.