The overall structure and working principle of a S3C2410 router

　　0 Introduction

　　It is predicted that the global router market will reach 15.9 billion US dollars by 2015. The development of home routers is particularly rapid. Currently, the regions with the largest demand are North America and Europe, but Asia has become the fastest growing region in the home router market. Therefore, in the next few years, the demand for home routers in Asia will be very huge.

　　Traditional routers will continue to exist in the market for a while due to their low prices, but the development trend of routers is intelligence and networking, which are the characteristics of routers represented by ARM and MIPS cores. Therefore, ARM core routers will occupy a place in the home router market in the near future. And with the popularization of ARM core technology, ARM core routers will have a higher cost performance and will be more competitive than other home routers.

　　1 ARM Technology

　　ARM neither produces nor sells chips, it only sells chip technology licenses. The main technologies of embedded ARM include: ARM processor architecture and ARM processor instruction set, storage system and exception interrupt processing.

　　(1) ARM architecture: A T variant was added, which can switch the processor state to Thumb state, in which the instruction set is a 16-bit Thumb instruction set.

　　(2) ARM processor instruction set: The ARM instruction set can be divided into six categories: jump instructions, data processing instructions, program status register transfer instructions, Load/Store instructions, coprocessor instructions, and exception interrupt generation instructions [1].

　　(3) ARM storage system: The architecture of the ARM storage system varies greatly to meet the needs of different embedded application systems. The simplest storage system uses a flat address mapping mechanism, just like some simple single-chip systems, the address space allocation method is fixed, and all parts of the system use physical addresses. Some complex systems may include one or more of the following technologies to provide a more powerful storage system.

　　(4) Abnormal interruption: When an abnormal interruption occurs, the system will jump to the corresponding abnormal interruption after executing the current instruction. When the abnormal interruption program is executed, the program returns to the next instruction of the interruption instruction.

　　2 Routers

　　(1) Central Processing Unit: The CPU of a router is responsible for the configuration management of the router and the forwarding of data packets, such as maintaining various tables required by the router and performing routing operations. The speed at which a router processes data packets depends largely on the type and performance of the CPU.

　　(2) Memory: Routers can use a variety of memories, including ROM (read-only), Flash (flash memory), DRAM (dynamic memory), etc.

　　(3) Interface: The physical connection between a router and various networks must be realized through an interface. The more advanced the router, the more types of networks it can connect to, and the more types of interfaces it has.

　　(4) Console port: Depending on the type of router, the specific interface method for connecting to the console is also different. There are two common types: a console port using DB-25 and a console port using RJ-45.

　　3 Design of S3C2410 Router

　　1. Overall structure diagram

　　The overall structural block diagram of the home S3C2410 router designed in this paper is shown in Figure 1.

　　(II) Main Function Implementation

　　(1) I/O part

　　1) Port Configurator (GPACON\'GPHCON) In S3C2410, most of the pins are multiplexed. Therefore, a function is required to be defined for each pin. The port controller (GPnCON) defines the function of each pin (n=A\'H). If GPFO\'GPF7 and GPG0\'GPG7 are used as wake-up signals in power-down mode, then these port configurations must be set in interrupt mode. [page]

　　2) Port Data Register (GPADAT\'GPHDAT) If the port is configured as an output port, data can be written to the corresponding bit of the GPnDAT register. If the port is configured as an input port, data can be read from the corresponding bit of the GPnDAT register.

　　3) Port pull-up register (GPBUP\'GPHUP) The port pull-up register controls the enable or disable of the pull-up register of each port group. When the corresponding bit is 0, the pull-up register of this pin is allowed; when it is 1, the pull-up register is disabled.

　　1) Data transmission operation These can be set through the linear controller (uLCONn).

　　2) Data reception: They are all set through the linear controller (ULCONn).

　　3) Baud Rate Generator: The baud rate is determined by the clock source (PCLK or UCLK) divided by 16 and the 16-bit divisor specified by the UART baud rate divisor register (UBRDIVn).

　　(3) Storage device components

　　Compared with Flash memory, SDRAM does not have the feature of retaining data when power is off, but its storage speed is much higher than Flash memory, and it has read/write properties. Therefore, SDRAM is mainly used for program operation space, data and stack in the system. When the system starts, the CPU first reads the startup code from the reset address OxO chip. After completing the system initialization, the program code is transferred to SDRAM to run to increase the system's operating speed.

　　NAND Flash and NOR Flash: NOR and NAND are the two main non-volatile flash memory technologies on the market. NOR is characterized by on-chip execution (XIP, eXecute In Place), so that the application can run directly in the Flash memory without having to read the code into the system RAM. NOR has high transmission efficiency and is very cost-effective in small capacities of 1~4MB, but its low write and erase speeds greatly affect its performance.

　　NAND structure can provide extremely high cell density, can achieve high storage density, and write and erase speed is also very fast. The difficulty of using NAND lies in the management of Flash and the need for special system interface. Performance comparison:

　　●NOR's read speed is slightly faster than NAND.

　　●NAND write speed is much faster than NOR.

　　●NAND's 4ms erase speed is much faster than NOR's 5s.

　　●Most write operations require an erase operation first.

　　●NAND's erase unit is smaller, and the corresponding erase circuits are less.

　　4 Conclusion

　　The S3C2410 router has 64M SDRAM and a high operating frequency of 203MHz, and mainstream embedded operating systems can be transplanted on it. Manufacturers can add wireless modules to the hardware and corresponding functional software to the software according to the needs of different users. Whether in terms of hardware or software, the S3C2410 router has a very strong performance advantage compared with the mainstream home routers on the market. With the continuous reform of network facilities, the transmission speed of the network will continue to accelerate. At the same time, with the integration of the network, network security issues have gradually emerged, and higher requirements have been placed on the stability of the router's operating system and its firewall. Therefore, these changes have led to higher and higher requirements for the router's load capacity and information processing capabilities, so the advantages of the S3C2410 router will be more obvious. The design of the 83C2410 router meets the development requirements of the router market and can meet the many requirements of network development on routers in information processing and security, and has certain theoretical and practical value.