Design and implementation of program-controlled filter based on single chip microcomputer and FPGA

　　A filter is a device used to eliminate interference noise. It can be used to effectively filter out a specific frequency point or frequencies outside the frequency point. It occupies a very important position in the field of electronics and has been widely used in signal processing, anti-interference processing, power systems, and anti-aliasing processing. As for the programmable filter, the biggest feature of the system is that its filtering mode can be selected by program control, and the -3dB cutoff frequency can be adjusted by program control, which is equivalent to a filter with multiple functions in one, and will have better application prospects. In addition, the system has the function of testing the amplitude-frequency characteristics, and displays the spectrum characteristics through an oscilloscope, which can intuitively reflect the filtering effect.

　　1. Scheme demonstration and selection

　　1.1 Design and demonstration of variable gain amplifier module

　　Solution 1: Digital potentiometer controls two-stage INA129 cascade. Use FPGA to control the digital potentiometer DS1267 to output different resistance values ​​as the feedback resistor of the high-precision instrument amplifier INA129. By controlling the digital potentiometer to change the amplification factor of INA129, the gain of the amplifier can be adjusted.

　　Solution 2: Use variable gain amplifier AD603. The variable gain amplifier is composed of an R-2R ladder resistor network and a fixed gain amplifier. The signal added to the input of the ladder network is attenuated and then output by the fixed gain amplifier. The attenuation is determined by the reference voltage added to the gain control interface. It can be controlled by a single-chip microcomputer, and the DAC generates an accurate reference voltage to control the gain, thereby achieving more accurate digital control.

　　Since the input sinusoidal small signal amplitude is 10mV, the voltage gain is 60dB, and the 10dB step is programmable, and the voltage gain error cannot be greater than 5%. In terms of accuracy, both solutions can be realized, and adding a stage of amplification after AD603 can also achieve a 60dB amplification factor. However, the internal structure of the digital potentiometer is complex and affected by capacitance. Connecting the post-stage to the op amp will bring unexpected consequences, so solution 2 is adopted.

　　1.2 Design and demonstration of filter module

　　Solution 1: Use digital filters. Use MATLAB's digital filters to design FIR or IIR filters. Digital filters have the advantages of high precision and good cutoff characteristics. However, FIR filters take up too many FPGA resources, and IIR filters require a lot of work to design and are not very stable. In addition, different parameters must be used to make the cutoff frequency adjustable, and the design requires a lot of software.

　　Solution 2: Use passive LC filter. Various types of filters can be built using inductors and capacitors. By referring to the relevant parameters in the filter design manual, it is relatively easy to design an ideal filter. However, if the cutoff frequency is to be adjustable, the only way is to change the inductor and capacitor parameters, and the hardware will be very complicated.

　　Solution 3: Use an integrated switched capacitor filter chip. The switched capacitor filter is a large-scale integrated circuit filter composed of MOS switches, MOS capacitors and MOS operational amplifiers. Driven by the clock frequency, its switched capacitor group can be equivalent to an equivalent resistor related to the clock frequency. When the external clock changes, the equivalent resistance changes, thereby changing the time constant of the filter, and thus changing the filtering characteristics. The switched capacitor filter can directly process analog signals without the need for A/D and D/A conversion like digital filters, which simplifies the circuit design and improves the reliability of the system.

　　In summary, this system adopts scheme 3, using the integrated chip MAX297 to realize the low-pass filter and using LTC1068 to realize the high-pass filter; it adopts scheme 2, using passive LC filter technology to realize the fourth-order elliptical low-pass filter.

　　2 System overall design and implementation block diagram

　　This system uses a single-chip microcomputer and FPGA as the control core, and is composed of a controllable gain amplifier module, a program-controlled filter module, and an amplitude-frequency characteristic test module. The system block diagram is shown in Figure 1. The input amplitude of 1V is attenuated by the voltage divider network and becomes a small signal with an amplitude of 10mV. It is amplified by 2 times by the OPA690 front stage, and plays the role of impedance transformation and isolation. At the same time, AD9851 generates a sinusoidal signal of a set frequency, which is sent to the back stage through the analog switch. The signal is amplified by the program-controlled AD603 with an adjustable gain of 0-60dB and then sent to the filter module. The filter module includes low-pass, high-pass, and elliptical filters, among which the low-pass and high-pass are controlled by the program to have a -3dB cutoff frequency adjustable in the range of 1-30kHz, with a step of 1kHz. The cutoff frequency of the elliptical filter is 50kHz. Then a specific filter signal is selected for output through the analog switch, and after effective value detection and A/D conversion, it is sent to the FPGA for amplitude-frequency characteristic testing, and then two DAC0800s are used to display the amplitude-frequency characteristic curve.

　　3 Main Function Circuit Design

　　3.1 Amplification module

　　The specific circuit of the amplifier module is shown in Figure 2. The first part is a voltage divider network, in which the first four resistors attenuate the input signal by 100 times and form a 51Ω impedance together with the internal resistance of the signal source, and the 51Ω at the back is a matching resistor. The second part uses OPA690 to amplify the small signal by 2 times, and at the same time plays the role of impedance transformation and isolation. Since the input impedance of AD603 is 100Ω, a 100Ω resistor is connected in series at the back for matching. The third part is the AD603 variable gain amplifier, and its gain increases linearly in dB as the control voltage increases. The reference voltage of pin 1 is obtained by calculating and controlling the output voltage of the DAC chip through the microcontroller, thereby achieving precise digital control. Gain G (dB) = 40VG + G0, where VG is the differential input voltage, ranging from -500 to 500mV; G0 is the starting point of the gain, which is different when connected to different feedback networks. A 5kΩ potentiometer is connected between pins 5 and 7 to change it.

　　3.2 High-pass filter module

　　LTC1068 is a low-noise, high-precision universal filter. When used for high-pass filtering, the cutoff frequency range is 1Hz to 50kHz, and there is no aliasing phenomenon up to 200 times the cutoff frequency. Since the four channels of LTC1068 are low-noise, high-precision, high-performance second-order filters, each channel can achieve the functions of low-pass, high-pass, band-pass and band-stop filters by connecting a few resistors externally. The specific circuit is shown in Figure 3. The Q value of port B is 0.57, and the Q value of port A is about 1. In the debugging of the circuit, it was found that the Q value of port A needs to be larger than the Q value of port B, otherwise the amplitude of the signal will rise at the cutoff frequency. [page]

　　The ratio of the clock frequency to the passband of LTC1068 is 200:1. Since the clock signal CLK is doubled internally by LTC1068, when the minimum cutoff frequency is 1kHz, the internal clock frequency is actually 400kHz. Therefore, a low-pass filter with a cutoff frequency of 450kHz is added after LTC1068 to filter out the noise and high-order harmonics caused by the frequency division.

　　3.3 Low-pass filter module

　　Use MAX297 to implement a low-pass filter. The switched capacitor filter MAX297 can be set as an 8th-order low-pass elliptical filter with a stopband attenuation of -80dB and a clock frequency to passband frequency ratio of 50:1. By changing the frequency of CLK, the filter -3dB cutoff frequency can be adjusted in the range of 1 to 20kHz in steps of 1kHz.

　　When using MAX297, it should be noted that when the signal frequency and the sampling resolution are the same, the switch capacitor group samples the same signal amplitude on the capacitor each time, which is equivalent to the case where the input signal is DC, so that the filter outputs a DC level. Similarly, when the signal frequency is an integer multiple of the sampling frequency, the same phenomenon will occur. For this reason, an analog low-pass filter should be added in front of it to effectively exclude high-frequency signals at and above the sampling frequency. Therefore, another MAX297 is used, and the cutoff frequency is set to 50kHz. The clock frequency is set to 2.5MHz. After it, a low-pass filter should also be added, and its cutoff frequency is 150kHz to filter out the high-frequency components of the signal and make the waveform smoother. The specific circuit is shown in Figure 4.

　　3.4 Fourth-order elliptic low-pass module

　　The system requires a fourth-order elliptical low-pass filter with an in-band fluctuation of ≤1dB and a -3dB passband of 50kHz. This is achieved using a passive LC elliptical low-pass filter. Use FilterSolution to simulate the filter, then simulate it again in Multisim and adjust the parameters of the capacitor and inductor to their nominal values. In addition, emitter followers are connected before and after the elliptical filter to avoid the influence of the previous and next stages. The specific circuit is shown in Figure 5.

　　4 System software design

　　The system software design consists of a single-chip microcomputer and an FPGA. Users can select high-pass, low-pass and elliptical filters through the interface display, set the cutoff frequency, and display the amplitude-frequency curve. The single-chip microcomputer mainly completes the user's input and output processing and system control, and the main functions of the FPGA are: controlling the AD9851 to generate a sweep signal, controlling the generation of the filter cutoff frequency clock signal, and controlling two D/A blocks to display the amplitude-frequency characteristic curve. The program flow chart is shown in Figure 6.

　　5. Test plan and test results

　　5.1 Amplifier Test

　　The frequency of the sine signal at the input of the amplifier is 10kHz, the amplitude is 10mV, and the gain is set to 10, 20, 30, 40, 50, and 60dB. The actual output amplitude is measured with an oscilloscope, and the actual gain is calculated, with an error of less than 1%. In addition, the passband of the amplifier is measured to be 1 to 200kHz.

　　5.2 Low-pass and high-pass filter test

　　Set the amplifier gain to 40dB, the filter to a low-pass filter, and the preset filter cutoff frequency to 1-30kHz in steps of 1kHz. Use an oscilloscope to measure the actual cutoff frequency, and the calculated relative error is less than 1.5%, and the total voltage gain at 2fc is less than 20dB. The high-pass filter test method is similar.

　　5.3 Elliptical filter test

　　The amplifier gain is set to 40dB, and the actual -3dB cutoff frequency and the total voltage gain at 200kHz are measured with an oscilloscope. The measured fc=50.0kHz, and the amplitude has almost decayed to 0 at 150kHz.

　　5.4 Amplitude-frequency characteristic and phase-frequency characteristic test

　　Measure the frequency characteristics of low-pass and high-pass filters, and display their amplitude-frequency characteristic curves on the oscilloscope, which are consistent with the set filtering mode and cut-off frequency.

　　6 Conclusion

　　The amplifier gain range of this system is 10-60dB, the passband is 1-200kHz, and the gain error is less than 1%. The filter cutoff frequency range is 1-30kHz, and the error is less than 1.5%. The cutoff frequency error of the elliptical filter is 0, and the amplitude is almost attenuated to 0 at 150kHz. The error mainly comes from the clock frequency. When the cutoff frequency is 20kHz, the highest clock frequency required is 2MHz, which cannot guarantee a good clock edge, and the clock frequency cannot be accurately controlled, as well as the nonlinear error of the amplifier. In addition, the amplitude-frequency characteristic tester is realized by using DAC0800 and the effective value detection circuit, and the overall performance of the system is good. Under the organic combination and coordinated control of the single-chip microcomputer and FPGA, the entire system works stably, has high measurement accuracy, and flexible human-computer interaction.