Hardware Design of Multipoint Video Conference Control Unit Based on IXP425 and DM642

Introduction
    "Conference video system" refers to a system that allows people or groups in different places to transmit sound, images and text materials to each other through communication lines and multimedia communication equipment to achieve instant and interactive communication, thereby achieving the purpose of traditional centralized conferences. The use of conference video allows participants in multiple venues to hear the voices of people in other venues and see the images of other venues. Participants can express their opinions and observe each other's images through audio/video transmission and communication. In addition, they can show physical objects and drawings to enhance the sense of presence. They can also transmit relevant documents, charts or discuss issues in a timely manner through fax or shared electronic whiteboards, shortening the spatial distance between participants, improving the atmosphere of the meeting, and making all participants feel as if they are in the same place. The
    conference video system is mainly composed of terminal equipment, transmission channels (communication networks) and multipoint control units MCU (Multipoint Control Unit). Among them, the multipoint control unit is the core part of the conference video system, and its function is equivalent to the switch in the computer network. The switch extracts audio, video, data and other information and signaling after synchronous separation of information flow from each conference site, and then sends the information and signaling of the conference site to each processing module to complete the corresponding audio/video mixing or switching, data broadcasting and routing selection, timing and conference control, and finally reassembles the various information required by the conference site and sends it to each conference TV terminal. This paper is based on the design of an embedded conference TV multi-point control unit for small and medium-sized users with low cost, stable operation, complete functions, large capacity, fast computing speed, good compatibility, good security, simple operation, and can run under 2M network bandwidth.
    The main functions of the conference video multipoint control unit (MCU) are:
    ① Media control, media processing: including audio and video extraction, audio and video re-encoding, mixing, switching, etc., data broadcasting and routing selection, voice excitation calculation and other required media functions;
    ② It can receive audio and video data forwarded by other multipoint control units, re-switch or mix audio/video, and then send it to the conference video terminal for decompression and decoding, and then restore it to sound, image and computer data for local output;
    ③ MCU and terminal follow the protocol (such as H.323, SIP, etc.) to connect;
    ④ MCU and terminal can receive control signals sent by each other and respond;
    ⑤ Network access function;
    ⑥ Parameters can be set through RS232.

1 Scheme design
    Scheme 1: The reference proposes a solution for implementing a multipoint control unit in a desktop video conferencing system based on TCP/IP protocol. The solution adopts a pure software structure, with low solution cost and short development cycle, but the solution has limited audio and video processing channels and poor image quality.
    Scheme 2: The reference proposes a DSP-642-based conference video hardware platform solution, and designs and implements a H. 264 protocol pixel domain multi-screen synthesis PCI communication module, video codec module, but the capacity is only 4 channels, the picture quality is average.
    Comprehensive comparison of the above two solutions, combined with the specific situation of the conference TV multi-point control unit MCU, the conference TV multi-point control unit MCU designed in this paper uses Intel embedded processor IXP425 as the main controller, 4 DM642 chips as data processing chips, and the main controller and data processing module use PCI bus for communication. This solution has a relatively short development cycle. Chip manufacturers such as TI and InteI provide complete software and hardware development kits. In addition, because the PCI bus is used to connect the main controller module and the data processor module, the data transmission speed is fast and the throughput is high.

2 System Design
    The system block diagram and the functional chips used are shown in Figure 1. The system is mainly composed of a control module and an audio/video processing module.

    The control module is composed of IXP425+CPLD on the board. It is responsible for the resource and information management of the board, and forwards the audio/video signals sent from the service board to the corresponding DM642 for processing. The board CPLD mainly realizes the functions of the board reset, clock detection, chip select signal control, register reading and writing, and board information. The audio/video processing module is completed by 4 DM642 chips on the board and is the core module of the board. There are two key factors that determine the performance of the audio/video processing module: the performance of the audio/video algorithm and the transmission performance of the PCI bus.
    In order to enhance the transmission performance of the PCI bus, it can be improved from the following two aspects: improve the transmission efficiency of the PCI bus; any device on the PCI bus can initiate transmission as the master device, so that the data transmission between DSP chips does not need to be forwarded through IXP425, saving bus bandwidth. [page]

2.1 IXP425 module
    The IXP425 module mainly includes the CPU minimum system, CPLD control module, debugging module, network management module, etc. The block diagram is shown in Figure 2.

    IXP425 has its own Expansion bus, which can connect flash, HPI bus devices, SDRAM and other devices to the internal ASHB. It is compatible with Intel/Motorola interfaces and has 8 banks of cs[7:0] for selection. Each block is 16 MB in size. If WinCE operating system is used, the Flash space is at least 20 MB. Therefore, the minimum system design uses two banks of cs0 and cs1 as system storage space. In order to leave enough storage space for program download mode, two 16 MB Flash are added. The Flash connection is shown in Figure 3.

    Since IXP425 has a built-in dedicated SDRAM controller, according to its interface principles and taking into account the fact that the platform has a certain margin for computing performance, the design of the SDRAM part in the minimum system uses two 32 MB SDRAMs, and the hardware is compatible with the 128 MB SDRAM design.

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2.2 Network port design
    IXP425 has three network processors NPE working in parallel with the XScale core, which can provide two MII interfaces to the outside. The principle of parallel operation makes the network processing performance better and supports 802.3 protocol content. The standard MII interface only needs an external PHY physical interface chip. The platform uses Intel's LXT972A to complete the interaction with the external data. Of course, the use of transformers is also necessary. The TG110-S050N2 produced by HALO is used to connect to the RJ45 interface. The connection diagram is shown in Figure 4. Since the IXP425 has a built-in MAC controller, the perfect MII interface makes the platform's network application relatively simple and targeted.

2.3 Audio/Video Processing Module Design
2.3.1 PCI Interface Design
    The IXP425 PCI controller has four DM642 chips mounted on the outside, and the bus is 33MHz. The connection diagram is shown in Figure 5. The IXP425 PCI bus mainly completes the boot loading of DM642, chip configuration management, PCI bus arbitration and media stream scheduling. The DM642 chipset mainly completes the encoding of audio/video media streams and audio/video synthesis. The current capacity is 4-channel audio/video synthesis, the video algorithm is H. 264, and the voice algorithm is AAC, G. 723.1, etc.

    Among them, DM642A occupies PCI time slot 1 of IXP425, DM642B occupies PCI time slot 2 of IXP425, DM642C occupies PCI time slot 3 of IXP425, and DM642D occupies PCI time slot 4 of IXP425. The corresponding pins with differences are interconnected as follows: DM642A corresponds to the PCI pin of IXP425. The PCI interrupt control signal is converged by CPLD and reported to CPU. CPU judges the interrupt event of peripheral PCI device by reading the interrupt register inside CPLD.
2.3.2 Minimum system design of audio/video processing module
    EMIFA allows seamless connection of multiple SDRAMs. Since the selected SDRAM size is 64 MB, according to the interface criteria of DM642 EMIFA, the minimum system of DM642 is shown in Figure 6.

    The chip selection is completed by CE0. After selecting two 16MB SDRAMs for bit expansion, the maximum addressing space is 32MB. The row address selection is A[3:10], the column address selection is A[3:14], and the block selection (bankselect) is A[15:16]. Therefore, the DM642 address lines A[3:16] are used. The DM642 core works in 50M×12 Hz mode, the EMIF interface works at 25M x 5.33 Hz, and the PCI interface works at a clock frequency of 33 MHz.

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2.3.3 Flash Design
    IXP425 has an external Flash to store the BOOT program. After the chip is started, the image required by IXP425 is imported from the large-capacity Flash into the memory. The DSP program is not configured with a separate Flash memory. IXP425 imports the DSP program into its own RAM through the PCI bus for operation. IXP425 is the master device of the PCI bus, and other DSP chips are slave devices.
    The process of IXP425 starting DSP through PCI bus is as follows:
    ① The configuration pin of DSP is set to PCI BOOT mode (AEA[22:21]=01, [PCI_EN:TOUT0/MAC_EN]=10)
    ② IXP425 releases the reset pin of DM642 through CPLD, and DM642 enters the installation state;
    ③ IXP425 configures the PCI register of DM642 through PCI bus;
    ④ IXP425 sets the memory and I/O space of DM642;
    ⑤ IXP425 imports the BOOT program of DM642 into the internal RAM of DM642, with the starting address being 0;
    ⑥ IXP425 accesses the memory space of DM642 and writes the program into the memory of DM642. The page register (DSPP) of DM642 enables IXP425 to access all the space of DM642;
    ⑦ IXP425 sets the DSPINT bit of the HDCR register of DM642 to 1, releasing DM642 from the installation state;
    ⑧DM642 starts running the BOOT program from address 0.
2.3.4 OPLD Design
    The specific functions completed by the single-board CPLD are as follows: single-board IC reset control, interrupt processing, clock detection, clock frequency division, clock timing (clock synchronization), chip selection decoding, and I/O expansion. The single board uses a CPLD, and the CPLD resources are required to be used only 70%, reserved for future upgrades and to prevent wiring tension.
2.4 Clock Design
    (1)
    The output of the PCI clock 33 MHz crystal oscillator is divided into 8 paths after passing through a BUF: one path is given to the CPLD as a detection clock; one path is given to the OSC-IN of the IXP425 as the chip working clock; one path is given to the EX_CLK pin of the IXP425 as the Expansion bus clock; one path is given to the PCI of the IXP425 as the PCI clock; and the remaining 4 paths are given to the PCI clock driver.
    (2) The Ethernet and SDRAM clock
    50 MHz crystal oscillator is the main clock of the CPLD. After being divided by 2, the clock is given to each Ethernet chip as the main clock of each chip. There is no synchronization requirement for each clock. The DM642 SDRAM clock is obtained by the ICS512 frequency multiplication, and the IXP425 has a strong driving capability of SDCLK_OUT, which can directly drive the 4 SDRAMs to work.
2.5 Single-board power supply design
    The power supply block diagram is shown in Figure 7.

2.6 JTAG Link
    The JTAG of the single-board CPU and CPLD are chained separately to facilitate loading and debugging. Four DM642 chips are connected into a daisy chain. The hardware is compatible with each chip being debugged separately. The daisy chain block diagram is shown in Figure 8.

3 Hardware Debugging
    The hardware part of this multi-point control unit mainly performs the following debugging:
    ① Power supply and reset module debugging: Weld the power supply module chip and peripheral circuits, and test whether the +5 V, 3.3 V, 1.4 V, and 1.3 V voltage outputs are normal. After the voltage output is normal, weld the reset circuit components, observe whether the reset voltage and duration meet the design requirements after power-on, and use an oscilloscope to measure whether the level and duration of the reset signal are consistent with the design. After power-on, pay attention to whether the voltage conversion chips are hot. If not, immediately disconnect the power supply for inspection.
    ② Minimum system debugging: Weld the IXP425 chip, DM642 chip, CPLD, SDRAM, Flash, JTAG interface and peripheral components of each module circuit on the board. Use an amplifier to carefully check whether there are short circuits, open circuits, cold soldering, leaking soldering, and false soldering. After no problems, power on, measure whether the working voltage of each chip is normal, and use an oscilloscope and frequency meter to measure whether the working clock of each module is normal. Use the JTAG port to connect the hardware to the computer. After configuring the control register, test whether the SDRAM read and write functions are normal, and whether the Flash erase and write functions are normal. If it does not work properly, check the timing signal, hardware connection, etc.
    ③ PCI bus debugging: Test whether the data transmission between each functional module is normal, such as IXP425 reading and writing 4 DM642s, reading and writing data between D642, etc., which requires testing with a computer, oscilloscope, spectrum analyzer, logic analyzer, etc.
    ④ Network transceiver module debugging: Solder LTX972A and peripheral devices. Check whether the connection between the MII interface of IXP425 and the LTX972A chip is normal, and test whether the network transceiver module can communicate data with the local PC through the network port through the LTX972A test program provided by Intel.

4 Conclusion
    The design of this multi-point control unit has the following features:
    ① Design of non-PC embedded conference video multi-point control unit;
    ② Internally adopts PCI bus connection to solve the problem of sudden large data transmission and synchronization of various data processing modules within the conference video multi-point control unit;
    ③ Design of multiple parallel data processing modules.