Design and application of embedded SMI network converter based on ARM and uC/OS

    introduction

    At present, with the rapid development of the Internet and embedded systems, more and more industrial measurement and control equipment have adopted network access functions as their default configuration to achieve remote monitoring of equipment and distributed information processing. However, a large number of industrial field equipment do not yet have network interfaces. In the development of the IP113F fiber optic transceiver monitoring system, the lower computer communicates with the SMI of the fiber optic transceiver through the single-chip microcomputer to achieve monitoring, and the upper and lower computers transmit data through the RS-232 interface. Due to the short transmission distance of the serial port, the staff have to go to the site every day to check and diagnose the data, which is very annoying. In view of this situation, it is necessary to design a data transmission module from SMI to Internet to remotely monitor the operating status of the fiber optic transceiver.

    IP113F Chip Introduction

    The IP113F chip is an ultra-low power fiber transceiver with network management function, supporting 3.3VI/O. It mainly operates two sets of independent registers through SMI (MDC, MDIO) to monitor or reset the working status of the local or remote fiber transceiver. Users can access the registers through the serial management interface, as shown in Figure 1. Since the address of IP113F is a 5-bit binary code, a management unit can simultaneously hang up to 32 (25) IP113F. Data is transmitted bit by bit on MDIO, which occurs on the rising edge of MDC. The data communication protocol on MDIO is shown in Table 1. When SMI is in idle state, MDIO is in high impedance state, and the management unit sends 32 consecutive "1" and "01" signals on MDIO to initialize the MDIO interface.

    Overall functional design

    The basic function of the system is that 32 fiber optic transceivers communicate with the remote host computer through the same SMI network converter at the same time, as shown in Figure 2. The specific work completed by the converter is to receive the test data sent by the local or remote fiber optic transceiver, automatically identify its length and source, convert it into network data format, and send it to the host computer through Ethernet. At the same time, it receives the control information sent by the host computer through Ethernet, and automatically identifies the target it sends, and then sends it to the corresponding fiber optic transceiver through the SMI port. According to actual needs, the IP address of the SMI network converter can be configured in the host computer through Ethernet.

    Hardware structure design

    The hardware circuit of the converter uses an embedded processor LPC2214 chip based on the arm7 core for overall control. The LPC2214 chip has 256KB of high-speed FLASH and 16K on-chip SRAM. In order to meet the requirements of data cache during communication and a certain system operation space, the 512KB SRAM is expanded by using IS61LV25616AL outside the chip. In addition, through the IIC bus, a 256-byte EEPROM is expanded outside the chip to save the set IP address. The 10M full-duplex Ethernet controller RTL8019AS chip is selected to complete the network communication function, and the HR61101 chip acts as a network card transformer. The general I/O port, P0.5 and P0.6 simulate the communication timing of SIM to collect data for IP113F. The overall hardware circuit of the circuit is shown in Figure 3.

    LPC2214 has an external memory interface, which can expand 4 banks of memory groups (Bank0~Bank3), and the chip select signals of Bank0~Bank3 are CS0-CS3 respectively. In this design, Bank0 is used to expand SRAM, and Bank3 is used to expand RTL8019AS module. Since LPC2210 chip is an 8/16/32-bit microprocessor, it can accept 16-bit data width reading and writing. In the design, the 16-bit I/O pin IOCS16B of RTL8019AS chip is connected to a high level to realize the reading and writing of the content of the control register in 16-bit operation mode. Compared with the design using single-chip microcomputer as processor, the system operation efficiency is improved. By connecting the 65-pin JP of RTL8019AS to a high level to select the jumper working mode, that is, the I/O and interrupt of RTL8019AS are determined by the jumper, there is no need to expand the EEPROM 93C46 chip to store information to control the I/O and interrupt of RTL8019AS, which reduces the connection and improves the stability of high-frequency circuit. When RTL8019AS works in jumper mode, its base address is 0X300. Since the working power supply of RTL8019AS is 5V and the I/O voltage of LPC2210 is 3.3V, a 470Ω protection resistor is connected in series on the bus connection.

    System software design and implementation

    Introducing RTOS

    Fiber optic transceiver data acquisition requires high real-time performance. If the traditional front-end and back-end design methods are used, it will be too complicated and the real-time performance cannot be guaranteed. The use of real-time operating system RTOS can solve this problem. μC/OS-II operating system is a source code RTOS with the characteristics of short and powerful code and easy to learn. It is an ideal choice for this design. [page]

    Selection and reduction of TCP/IP protocols

    In order to enable the SMI converter to have Ethernet access function, the TCP/IP protocol must be embedded in the arm processor. Referring to the open system interconnection (OSI) model, the TCP/IP protocol embedded in the ARM adopts a simplified four-layer model, namely the link layer, network layer, transport layer, and application layer. According to actual needs and combined with the processing power of the arm microprocessor, the complete TCP/IP protocol is comprehensively cut in the design. The link layer consists of the underlying protocol that controls the data transmission between different machines on the same physical network. The driver of RTL8019AS is implemented in this layer; in the network layer, only the ARP request is responded to for the ARP packet, RARP is cancelled, and only the simplest mapping cache table of IP address and MAC address is maintained and refreshed regularly; for the transport layer, considering the data transmission security of the designed system, the TCP protocol is selected in the design; for the application layer, the HTTP protocol is cut out, and its function is replaced by setting the control interface on the host computer.

    Through the above tailoring, a suitable TCP/IP protocol is obtained. The tailored TCP/IP protocol is embedded into the operating system μC/OS-II, and API interface functions are provided for application programs to call, so that arm can quickly send and receive network TCP data packets without conflict, meeting the requirements of industrial measurement and control systems for real-time and reliability.

    Solving key problems

    When the SMI serial port and Ethernet communicate bidirectionally, if the data transmission rates of both parties are in a synchronized state, that is, the receiving rate is equal to the sending rate, the system can forward the data immediately. However, in most cases, the data transmission rates of the sending and receiving parties are not consistent. Compared with Ethernet, the serial port is a slow connection, which may cause data loss. Therefore, a circular queue must be defined in the system as a buffer for data transmission and reception. In this system, two 1024-byte circular queues are defined as buffers for data transmission and reception, one is the serial port receiving buffer and the other is the Ethernet receiving buffer. Ethernet reception is triggered by interrupts. Relatively speaking, the sending tasks of the serial port and Ethernet have a lower priority. The received data cannot be forwarded immediately, but is temporarily stored in the circular buffer. As shown in Figure 4, Head and Tail point to the head and tail of the queue respectively. When Head=Tail, it means the queue is empty, (Head+1)Mod 1024=Tail means the queue is full, and the size of the free buffer can also be calculated by the Head and Tail pointers.

    The serial communication protocol of the transceiver distinguishes the source address and the destination address by adding the local/remote and transceiver numbers to verify the data. Since the IP address of the converter is mainly set by the host computer through Ethernet, a command header is added to the Ethernet data frame to distinguish whether the setting is IP data or data communicating with the transceiver.

    Software system implementation

    The entire software design of this system consists of an operating system and a series of user applications. The system creates a startup task TaskStart(), which is mainly responsible for the initialization of the system hardware, including the initialization and startup of the clock, the startup of the interrupt, the initialization and startup of RTL8019AS, etc., and divides each application task. According to the importance and real-time nature of each task, the entire module is divided into 6 application tasks with different priorities, namely IP address setting, receiving protocol conversion, sending protocol conversion, NET sending, SMI sending, and SMI acquisition.

    Execution of tasks

    After the tasks are divided, each task has its own stack space and competes with each other for the right to use the CPU. Once it obtains the right to use the CPU, it will run independently to complete a specific function.

    This system uses the TCP communication mode with arm as the server and PC as the client, and the host computer actively requests to connect to arm. Before establishing communication between the serial port and Ethernet, the IP address setting task must be called first to initialize the communication parameters of the IP address, subnet mask, gateway and SMI port.

    The functions implemented by SMI port communication include SMI sending and SMI collection. The SMI collection task has a lower priority. If no related events occur after multi-task scheduling, the system will continue to run the SMI collection task. If the status of the local or remote IP113F changes, the data will be sent to the remote host computer after protocol conversion. SMI sending runs independently as a separate task. The SMI sending task requires the system scheduler to notify whether there is data to be sent in the buffer. If there is no data to be sent, the task will be suspended and the system will run other tasks, as shown in Figure 5.

    The Ethernet communication module consists of Ethernet data transmission and reception and protocol conversion. Data reception is implemented in the interrupt service program of RTL8019. Ethernet data transmission, reception protocol conversion and transmission protocol conversion are run as independent tasks. The Ethernet data transmission task also requires the system scheduler to notify whether there is data to be sent in the buffer. Protocol conversion mainly implements the parsing of received data messages and adding protocol headers to the data to be sent. When programming, you can directly call the API function embedded in the TCP/IP protocol to layer the data messages.

    Synchronization and scheduling between tasks

    Usually, the task of a multitasking operating system is an infinite loop with no return value. If no higher priority task enters the ready state, the current task will not give up the right to use the CPU. In order to achieve the normal operation of the operating system and the synchronization of related events, the communication between tasks and the setting of event flags must be handled correctly. The functional structure of the system is shown in Figure 6.

    After the system performs multi-task scheduling, the high-priority task is blocked due to the application of a certain resource and enters the suspended state, and the system runs the SMI acquisition task with a lower priority. Each event is assigned a semaphore, and once the event occurs, the task enters the ready state. When the receive interrupt occurs, the protocol conversion task is started, and this process is implemented through the semaphore communication mechanism. The receiving protocol conversion task first parses the data from the host computer, and then sends it to the SMI send queue or EEPROM send queue according to the command head of the data, and then starts the corresponding SMI send task or IP setting task. The sending protocol conversion task converts the protocol of the data collected by the SMI, stores it in the Ethernet send queue, and then notifies the NET send task to send the data to the host computer, thereby ensuring the synchronization of tasks and events.

    Conclusion

    The SMI network converter designed in this paper realizes the function of the host computer monitoring 32 pairs of local/remote fiber transceivers at the same time. The LPC2214 chip is used in the design to overcome the problems of resource shortage and limited processing power brought by the original 8-bit single-chip processor. In terms of software, the TCP/IP protocol is cut down, which greatly simplifies the complexity of programming. The embedded μC/OS operating system greatly improves the real-time performance of the system. The system runs well and works stably. It can be applied to other serial port devices with a slight change in the software, and has broad application prospects.