Design of work and rest alarm controller

In daily work and study, it is often necessary to control the work and rest time in order to regulate the work, study, rest and other work and rest order. This article uses the 51 series single-chip microcomputer to realize the control design of the campus work and rest time. It has completed the control of up to 40 bell ringing times per day for the work and rest. At the same time, it has the functions of adjusting and displaying the daily time of the controller, setting the bell time, and not losing the data when the power is off.

System hardware structure

In order to realize the above functions, the hardware mainly uses AT89C52 single-chip microcomputer to realize the control of the whole system, and uses DS1302 clock chip to complete the timing control of the controller time. At the same time, 24C02 serial storage chip is used to save the bell time control parameters to avoid power failure. 8 buttons are designed for time adjustment and bell time setting and adjustment, and the static display method is used to control 6 digital tubes to complete the setting and adjustment of time and bell time points. The relay control circuit is used to complete the weak current to the strong current 220V to complete the power on and off control of the bell and control the ringing sound. The specific circuit diagram is shown in Figure 1.

Figure 1 Hardware schematic diagram of the work and rest bell controller

MCS-51 simulates IIC bus

In order to prevent the data loss of the bell time point after power failure, this design uses a 256-byte EEPROM chip CAT24WC02 with IIC protocol serial communication as a storage chip. The IIC protocol allows system designers to connect up to 128 different devices with only two wires, which greatly saves the interface wires of the microcontroller. The impedance matching problem can be solved by adding a 10kΩ pull-up resistor to each of the two wires. IIC devices determine their own addresses through their own hardware connection methods. For example, the address of the CAT24WC02 chip in this design is 0000. For microcontrollers without IIC bus interfaces, any two wires can be used to simulate the IIC bus timing. In this design, P3.3 and P3.4 are used to simulate SCL and SDA lines respectively. When SCL is at a high level, SDA changes from a high level to a low level to form a start condition. All operations on the IIC bus must start with the start condition; when SCL is at a high level, SDA changes from a low level to a high level to form a stop condition. At this time, all operations on the IIC bus are stopped; when SCL is low and the SDA line level changes, the data is output from the CPU to the IIC bus; when SCL is high and the SDA line level remains unchanged, the CPU reads the data on the IIC bus; when SCL is high and the SDA level changes, the IIC bus has a start condition or a stop condition; data transmission is carried out in a sequence of 8. The IIC device sets SDA to a low level at the 9th clock cycle, that is, sends a confirmation (acknowledgement) signal ACK, indicating that the data has been received. The following 4 common functions are used here:

void I2cStart(); //Generate start signal

void I2cStop(); //Generate a stop signal

void I2cSendByte(uchar ByteData); //Send a byte of data

uchar I2cReceiveByte(); //Receive a byte of data

DS1302 clock circuit

DS1302 is a high-performance, low-power, RAM-equipped real-time clock chip launched by Dallas, USA. It can time the year, month, day, week, hour, minute, and second, and has leap year compensation function. The working voltage is as wide as 2.5V~5.5V. It uses a three-wire interface to communicate synchronously with the CPU, and can use burst mode to transmit multiple bytes of clock signals or RAM data at a time. DS1302 has a 31-byte RAM register for temporary data storage. The DS1302 control circuit diagram is shown in Figure 1. VCC1 is the backup power supply, and VCC2 is the main power supply. When the main power supply is turned off, the clock can also keep running continuously. DS1302 is powered by the larger voltage of VCC1 or VCC2. When VCC2 is greater than VCC1+0.2V, VCC2 powers DS1302. When VCC2 is less than VCC1, DS1302 is powered by VCC1. X1 and X2 are oscillation sources, and an external 32.768kHz crystal oscillator is connected. RST is the reset/chip select line. All data transfers are started by driving the RST input high. The RST input has two functions: 1. RST turns on the control logic, allowing the address/command sequence to be sent to the shift register; 2. RST provides a means to terminate the transmission of single-byte or multi-byte data. When RST is high, all data transfers are initialized, allowing the DS1302 to be operated. If RST is set to a low level during the transmission process, the data transfer will be terminated and the I/O pin will be in a high-impedance state. When powered on, RST must remain low before VCC ≥ 2.5V.

The control word of DS1302 is shown in Figure 2. The highest bit (bit 7) of the byte must be logic 1. If it is 0, data cannot be written to DS1302. If bit 6 is 0, it means accessing calendar clock data, and 1 means accessing RAM data; bits 5 to 1 indicate the address of the operation unit. The lowest bit (bit 0) is 0, indicating a write operation, and 1 indicates a read operation. The control byte is output from the lowest bit. Data is written to DS1302 at the rising edge of the next SCLK clock after the control instruction word is input, and data input starts from the low bit. Similarly, the data of DS1302 is read out at the falling edge of the next SCLK pulse following the 8-bit control instruction word, and the read data is from the low bit to the high bit.

DS1302 has 12 registers, 7 of which are related to the calendar and clock. The data bits stored are in BCD code format. The calendar and time registers are shown in Figure 3. DS1302 also has year register, charging register, clock burst register and RAM and other related registers. The clock burst register can read and write all register contents except the charging register in sequence at one time. DS1302 RAM-related registers are divided into two categories. One is a single RAM unit, a total of 31, each unit is configured as an 8-bit byte, and its command control word is C0H~FDH, where odd numbers are read operations and even numbers are write operations; the other is a RAM register in burst mode, in which all 31 bytes of RAM can be read and written at one time. The command control word address is FEH for write operations and FFH for read operations.

Figure 2 DS1320 command control word

Figure 3 DS1320 clock, calendar registers and control words [page]

System software implementation

Main program flow

The main program of this system considers that up to 40 bell time points can be set every day, and the time points are accurate to minutes. Therefore, each time point information includes two bytes for storing the hour and minute, and a total of 80 bytes are required as the bell time point storage buffer. This buffer is defined in the form of an array in the AT89C52 memory. At the same time, when the bell time point is set, this data is saved to the CAT24WC02 serial chip to prevent power loss. At the next startup, the data is first read from the CAT24WC02 chip and saved to the corresponding data buffer. Running the main program first reads the clock chip time data and displays the relevant information on the digital tube, then compares the current time with each bell time point to see if the bell needs to be rung, and finally performs keyboard information processing to complete the time setting and bell time point setting and other related operations. The specific process is shown in Figure 4.

Figure 4 Main program flow chart

Alarm time setting program design

This design uses a total of 8 buttons, among which the time setting button and the alarm setting button are multiplexed buttons. As shown in Figure 4, when the main program is running, pressing the corresponding button will cause the program to enter the time setting or alarm time setting program. In the alarm time setting program, these two buttons are also used to add alarms and delete alarm settings respectively. When the 6-digit digital tube display information is in a flashing state, pressing the add button at this time means adding a new alarm time point, and pressing the delete button means deleting the corresponding alarm time point. If the 6-digit digital tube display information is not fully flashing, these two buttons will not work. The left and right shift buttons are used to select the data bit (hour or minute) to be set, respectively. After selecting the corresponding bit, the corresponding data enters a flashing state. At this time, operate the increase or decrease button to enter the corresponding value setting. When only the alarm time sequence number flashes, the increase and decrease buttons have the function of querying all alarm time points in sequence. After the information is set, when the confirmation key is pressed, it means that the information setting is completed. At this time, the set alarm information will be uniformly sorted from small to large (displayed from small to large when used for query), and then saved to the corresponding memory of the microcontroller and the CAT24WC02 serial EEPROM to prevent power loss. If the cancel key is pressed, it means that the set information is abandoned. At this time, the original alarm time information is read from the CAT24WC02 serial EEPROM to the corresponding buffer of the microcontroller's corresponding memory. The specific flow chart is shown in Figure 5.

Figure 5 Main program flow chart

The display program void Display is responsible for the alarm time information display program. The data when the alarm is set is placed in the temporary display buffer and passed to the display program for further processing together with its flashing state value, so as to determine which digital tube display information flashes. The flashing state value FlagBit has 5 value parameters, namely 0, 1, 2, 3, and 4, where 0 means no flashing, 1 means flashing of the alarm time minute value, 2 means flashing of the alarm time value, 3 means flashing of the alarm time sequence number, and 4 means flashing of all displayed values ​​together. The specific flashing control is to continuously invert the flashing flag in the timer interrupt service program, and the display program controls the flashing according to the changes of this flag.

The time setting processing program mainly updates the data of DS1302 after setting the time by pressing buttons. The specific process is similar to the alarm setting program and will not be described in detail due to space reasons.

Conclusion

In the initial stage of the experiment, this design was mainly completed through simulation software. Due to the influence of experimental conditions, the digital tube display part was completed using a static display method. If cost savings are considered, this design can also be completed using a dynamic display circuit or a serial display circuit in the actual circuit.