Principle design of biochip detection circuit using QCM sensor

The original design of this system is 8-channel QCM detection, that is, 8 sets of identical oscillators with MAX913 chip as the core are used, which are inverted by 2 CD4069 inverters and sent to the D end of 4 frequency differencers 74LS74. Each frequency differencer 74LS74 has 2 D flip-flops inside. 2 6M high-precision active crystal oscillators are converted into 8 6M output signals after passing through the clock chip CDCV304, and sent to the CLK end of 4 frequency differencers 74LS74 respectively. The frequency signal after the frequency difference of 4 frequency differencers 74LS74 is sent to the I/O port of the programmable logic device EPM570GT100C3 chip. EPM570GT100C3 is used as a frequency meter here, which is realized through software programming. The recorded difference frequency is sent to the 51 single-chip microcomputer AT89S52 through the 8-bit data line. At the same time, AT89S52 controls EPM570GT100C3 to select which channel. The data processed by AT89S52 is sent to the host computer through the 232 serial port. The QCM coagulation sensor is a non-mass response sensor. It uses the high sensitivity of the quartz crystal oscillation frequency change to the density and viscosity changes of the crystal system to detect the changes in the system properties. The QCM coagulation sensor detects the red blood cell aggregation time and sedimentation rate by causing the sensor response through the change of the red blood cell impedance characteristics. Therefore, a coagulation analyzer was developed using the biochip detection technology based on the QCM sensor. The

quartz crystal oscillation frequency is highly sensitive to the changes in the crystal surface mass load (mass effect) and the physical properties of the reaction system such as density, viscosity, conductivity, etc. (non-mass effect). It has a sub-ng level mass detection capability, and its sensitivity can reach 1ng/Hz.

Take one channel as an example to design the biochip detection circuit based on QCM sensor. Since one channel uses fewer logic gates, the programmable logic device EPM7128LC84-10 is selected. Figure 1 shows the overall design block diagram of the system. Figure 1 Overall design block diagram of the system

Hardware Design

1. Quartz crystal oscillation and difference frequency circuit

In order to ensure that the QCM can oscillate after the biological reagent is dripped, a relatively special self-excited oscillator circuit must be used. The ordinary oscillator circuit composed of an inverter is not easy to start. The self-excited oscillator is usually composed of three parts: a basic amplifier circuit, a positive feedback network, and a frequency selection network. In the quartz crystal oscillator circuit, the quartz crystal is the main component of the positive feedback network and is also a frequency selection network. The conditions can only be met at the inherent resonant frequency of the quartz crystal oscillator. According to this principle, an oscillator with the MAX913 chip as the core is used. Its output is TTL level, which is convenient for signal acquisition of single-chip microcomputers or programmable logic devices. The square wave signal output by the QCM oscillator circuit for measurement is sent to the D end of the difference frequency device 74LS74, and the square wave signal output by the high-precision 6M crystal oscillator for reference is sent to the CLK end of the difference frequency device 74LS74. The difference frequency signal obtained is sent to the programmable logic device for counting. The purpose of using the difference frequency is to reduce the frequency input to the programmable logic device EPM7128. The quartz crystal oscillator and difference frequency circuit are shown in Figure 2. Figure 2 Quartz crystal oscillator and difference frequency circuit 2. The difference frequency signal of EPM7128 and AT89S52 after passing through the difference frequency device 74LS74 is output from the 5th pin of 74LS74 to the 6th pin I/O port of the programmable logic device EPM7128. Since the pins of programmable logic devices are relatively flexible and have the ability to be erased and programmed, when modifying the original design, it is only necessary to modify the original design file and reprogram the programmable logic device chip, without modifying the circuit layout or reprocessing the printed circuit board. This greatly improves the flexibility of the system and has good confidentiality. Here, it is designed as a frequency meter through software programming. At the beginning of the measurement, the host computer sends a command to the 51 single-chip microcomputer AT89S52 through the serial port. AT89S52 first sends an RST reset command to the 22nd pin of EPM7128, so that EPM7128 starts to work and count frequency after resetting. The frequency measurement timing time is 100ms. After the timing is over, the 46th pin of EPM7128 sends an interrupt signal to the external interrupt 0 port (INT0) of AT89S52. After receiving the interrupt signal, the single-chip microcomputer sends 3 selection signals SEL0~SEL2 from P1 port P10~P12 to EPM7128. Since the EPM7128 is designed as a 32-bit counter, and the 51 single-chip microcomputer is an 8-bit machine, it is necessary to process the 32-bit data signal four times in a time-sharing manner, which is controlled by the selection signals SEL0~SEL2. Finally, the 8-bit data signal is output from EPM7128 to the P0 data port of AT89S52, and after being processed by the single-chip microcomputer, it is sent to the host computer through the serial port for final data processing and graphical interface display. The hardware circuit diagram of this part is shown in Figure 3. Figure 3 Control circuit of programmable logic device EPM7128 and 51 single-chip microcomputer AT89S52. The 14th and 15th pins of AT89S52 are connected to the crystal oscillator and capacitor to form the oscillation circuit of the single-chip microcomputer. The 4th pin is the reset terminal, which is controlled by IPM810. IPM810 has the functions of power-on reset, manual reset and undervoltage reset. AT89S52 uses a PLCC44-pin packaged chip device. The P1 port and reset port of the single-chip microcomputer AT89S52 are used for online programming. The at89isp software is used for online programming to burn the program. The 83rd pin of EPM7128 is the global clock, which is the clock signal for external work. The clock signal can be generated by an active crystal oscillator or a passive crystal oscillator plus an oscillator. The 14th, 71st, 23rd and 62nd pins of EPM7128 are TDI, TDO, TMS and TCK terminals, which are JTAG programming ports. EPM7128 also uses online programming to burn the program, using JTAG online programming. The other pins are basically I/O ports, which can be specified as needed. In this design, the programmable logic device EPM7128 and the 51 single-chip microcomputer AT89S52 are connected by 13 wires for data communication and control, among which OUTPUT0~OUTPUT7 are data communication, SEL0~SEL2 are the chip select control signals of AT89S52 to EPM7128, and INT is the interrupt control signal sent by EPM7128 to AT89S52. [page] Software Design The kernel program of the ALTERA programmable logic device EPM7128 in this system is written in Verilog HDL hardware description language, compiled using MAX+plusII10.1 compilation system or Quartus II 4.2 compilation system, and the design realizes functions such as frequency division, frequency counting, and data selection. The 51 single-chip microcomputer AT89S52 is programmed in a mixed manner of C language and assembly language, and compiled using Keil C51 compilation system. 1. The top-level circuit of the programmable logic device EPM7128 is shown in Figure 4. It consists of a frequency division module, a counting module, and a data selection module. The frequency division module and the counting module are written in Verilog HDL hardware description language, and the data selection module uses a graphical input method. The 12M oscillation signal is sent to the CLK terminal of the EPM7128, and after passing through the frequency division module, it becomes a 10Hz frequency signal to provide a reference time base for the counting module. AT89S52 provides a reset RST signal to the RST terminal of the EPM7128, so that the EPM7128 is reset and starts to record the frequency signal sent to the CLKX1 terminal of the EPM7128 by the frequency difference device. When the timing time is up, the output terminal INT of the EPM7128 sends an interrupt signal to notify the microcontroller to receive data. Since the timer of the counting module is 32 bits, the 8-bit data signal output from the output terminals OUTPUT7~OUTPUT0 of EPM7128 is selected to the P0 data port of AT89S52 through three 8-bit two-to-one data selectors under the control of the SEL0~SEL2 chip select signals given by the single-chip computer. Figure 4 Top-level circuit of the programmable logic device EPM7128 2. The frequency division module of the programmable logic device EPM7128 The purpose of the frequency division module is to divide the 12M frequency signal input from the 83rd pin of the programmable logic device EPM7128 into a 10Hz frequency signal to serve as the reference clock for the counting module, that is, the timing time is 100ms. 3. The 10Hz signal divided by the frequency division module is sent to the counting module of the programmable logic device EPM7128, which is added to the gate that can control the opening and closing time through the gate control circuit. The measured pulse is added to the input end of the gate in the counting module. When the frequency measurement starts, the counter is set to 0 first. After the gate signal arrives, the gate is opened to allow the measured pulse to pass through. The counter starts counting until the gate signal ends, the gate is closed, and the counting stops. Therefore, when the period of the gate signal is 1s, the number of measured pulses passing through the gate during the gate opening time of 1s is the frequency of the measured signal. In order to enable the host computer to obtain more data and accuracy, the period of the gate signal is set to 0.1s. The following is part of the program code of the counting module of the programmable logic device EPM7128: always @ (posedge CLK_1hz or negedge RST) begin if (!RST) begin CNT_EN=0; LOAD=1; end else begin CNT_EN=~CNT_EN; LOAD=~CNT_EN; end end assign CNT_CLR=~(~CLK_1hz&LOAD); ssign INT=LOAD; //Use the rising edge of LOAD to interrupt the microcontroller.













































always @(posedge CLKX or negedge CNT_CLR)
begin
if (!CNT_CLR) //When CNT_CLR is at a low level, OUT=0; counter clears
OUT=0;
else if (CNT_EN)
begin
OUT=OUT+1; //When the rising edge of CLKX arrives, the counter increases by 1
end end
always @(posedge LOAD) //When the rising edge of the latch signal LOAD arrives, execute the following statement
begin
FRE=OUT; //Assign OUT to FRE
end
endmoduleThe

key code of the counting module of the programmable logic device EPM7128 is given above. CLK_1hz represents the gate signal, CLKX represents the measured pulse, RST is the system reset signal, FRE is the pulse frequency data after latching, and INT is the interrupt signal to the microcontroller. These signals are the input and output signals in the counting module. There are several internally defined signals in the counting module, CNT_EN is the counting enable signal, CNT_CLR is the counting clear signal, LOAD indicates the latch signal, and OUT indicates the pulse frequency signal before latching. The gate signal is 10Hz, and the frequency measurement is performed every two clock cycles, that is, within every two clock cycles CLK_1hz, the CNT_CLR that arrives first for half a clock cycle is used for clearing; then, CNT_EN is valid within a clock cycle CLK_1hz for counting; finally, within the later half clock cycle, when the rising edge of LOAD arrives, the counting result is latched.

4. Program of 51 single-chip microcomputer AT89S52 The

51 single-chip microcomputer first initializes the timer, serial port and interrupt settings, sends a reset signal to EPM7128, and then enters the large loop program, waiting for external interrupts. When the EPM7128 timing time is up, an interrupt signal is sent to the external interrupt 0 of AT89S52. The program of AT89S52 jumps to the external interrupt, performs data processing, and gives the combination of selection signals SEL0~SEL2 respectively. It receives the data signal of EPM7128 in time-sharing mode and then sends it to the host computer through the serial port. Since the measured frequency will not exceed 10MHz, only 24 bits of data need to be read. Figure 5 is the flow chart of the interrupt program of external interrupt 0. Figure 5 Flow chart of the interrupt program of external interrupt 0 Experimental results First add 100 microliters of plasma (warm bath 180S) to the flow cell, rotate the screw to the scale 17.0, and then inject TT thrombin solution through the small hole on the side and then withdraw the syringe. Figure 6 shows the clotting experiment of plasma with a diameter of 6mm (plasma + TT thrombin = 100 + 100μl). This figure shows the result of directly sending the frequency of the 10MHz quartz crystal to the programmable logic device for counting when the quartz crystal is AT-cut, the electrode is a silver film, the base frequency is 10MHZ, and the crystal diameter is 6mm (no frequency difference device is used). Figure 6 Diameter 6mm plasma coagulation experiment QCM as a micro-mass sensor has the advantages of simple structure, low cost, large vibration Q value, high sensitivity, and measurement accuracy that can reach the nanogram level. It is widely used in chemistry, physics, biology, medicine, and surface science. Piezoelectric quartz crystal sensors are used for coagulation factor detection with the advantages of easy use, high accuracy and low cost, and have broad clinical application and promotion prospects.