Design of ESD protection structure for CMOS circuits

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Design of ESD protection structure for CMOS circuits [Copy link]

ESD (electrostatic discharge) is one of the most serious failure mechanisms in CMOS circuits, which can cause the circuit to burn itself. This paper discusses the necessity of ESD protection for CMOS integrated circuits, studies the design principle of ESD protection structure in CMOS circuits, analyzes the relevant requirements of the structure on the layout, and focuses on the design requirements of ESD protection structure in I/O circuits. 1 Introduction Electrostatic discharge can bring destructive consequences to electronic devices. It is one of the main causes of integrated circuit failure. With the continuous development of integrated circuit technology, the characteristic size of CMOS circuits is constantly shrinking, the gate oxide thickness of the tube is getting thinner, the area of the chip is getting larger, and the current and voltage that MOS tubes can withstand are getting smaller and smaller, while the peripheral use environment has not changed. Therefore, in order to further optimize the circuit's anti-ESD performance, how to make the effective area of the entire chip as small as possible, the ESD performance reliability meets the requirements, and no additional process steps are needed has become the main consideration for IC designers. 2 ESD protection principle The purpose of designing ESD protection circuit is to prevent the working circuit from becoming the discharge path of ESD and being damaged, and to ensure that when ESD occurs between any two chip pins, there is a suitable low-resistance bypass to introduce ESD current into the power line. This low-resistance bypass must not only absorb ESD current, but also clamp the voltage of the working circuit to prevent the working circuit from being damaged due to voltage overload. When the circuit is working normally, the anti-static structure is not working, which requires the ESD protection circuit to have good working stability and be able to respond quickly when ESD occurs. While protecting the circuit, the anti-static structure itself cannot be damaged. The negative effects of the anti-static structure (such as input delay) must be within an acceptable range, and the anti-static structure must be prevented from latching. 3 Design of ESD protection structure of CMOS circuit Most of the ESD current comes from outside the circuit, so the ESD protection circuit is generally designed next to the PAD and inside the I/O circuit. A typical I/O circuit consists of two parts: an output driver and an input receiver. ESD is introduced into the chip through PAD, so all devices in I/O that are directly connected to PAD need to establish an ESD low-resistance bypass parallel to it, introduce the ESD current into the voltage line, and then distribute it to each pin of the chip by the voltage line to reduce the impact of ESD. Specifically for the I/O circuit, that is, the output driver and input receiver connected to PAD, it must be ensured that when ESD occurs, a low-resistance path parallel to the protection circuit is formed to bypass the ESD current and immediately and effectively clamp the protection circuit voltage. When these two parts work normally, the normal operation of the circuit is not affected. Commonly used ESD protection devices include resistors, diodes, bipolar transistors, MOS tubes, thyristors, etc. Because MOS tubes are compatible with CMOS processes, MOS tubes are often used to construct protection circuits. NMOS tubes under CMOS process conditions have a lateral parasitic npn (source-p-type substrate-drain) transistor, which can absorb a large amount of current when turned on. By using this phenomenon, a protection circuit with a higher ESD withstand voltage can be designed in a smaller area. The most typical device structure is the gate grounded NMOS (GGNMOS). Under normal working conditions, the NMOS lateral transistor will not conduct. When ESD occurs, the depletion region of the drain and substrate will avalanche, accompanied by the generation of electron-hole pairs. Some of the generated holes are absorbed by the source, and the rest flow through the substrate. Due to the existence of the substrate resistance Rsub, the substrate voltage is increased. When the PN junction between the substrate and the source is forward biased, electrons are emitted from the source into the substrate. These electrons are accelerated by the electric field between the source and the drain, resulting in collision ionization of electrons and holes, thereby forming more electron-hole pairs, causing the current flowing through the npn transistor to increase continuously, and finally causing the NMOS transistor to have a secondary breakdown. At this time, the breakdown is no longer reversible, and the NMOS tube is damaged. In order to further reduce the voltage across the NMOS on the output driver during ESD, a resistor can be added between the ESD protection device and the GGNMOS. This resistor cannot affect the working signal, so it cannot be too large. Polysilicon (poly) resistors are usually used when drawing the layout. Only one-level ESD protection is used. When the ESD current is large, the tubes inside the circuit may still be broken down. When the GGNMOS is turned on, due to the large ESD current, the resistance on the substrate and the metal connection cannot be ignored. At this time, the GGNMOS cannot clamp the input receiving end gate voltage, because the voltage of the input receiving end gate silicon oxide layer reaches the breakdown voltage. It is the IR voltage drop between the GGNMOS and the input receiving end substrate. To avoid this situation, a small size GGNMOS can be added near the input receiving end for secondary ESD protection, and it can be used to clamp the input receiving end gate voltage, as shown in Figure 1.

Design of ESD protection structure for CMOS circuits

When drawing the layout, it is necessary to pay attention to placing the secondary ESD protection circuit close to the input receiving end to reduce the resistance of the substrate and its connection between the input receiving end and the secondary ESD protection circuit. In order to draw a large-sized NMOS tube in a smaller area, it is often drawn as a finger shape in the layout. When drawing the layout, the design rules of I/OESD should be strictly followed. If the PAD is only used as an output, the protection resistor and the NMOS with a short gate grounding are not needed. The large-sized PMOS and NMOS devices in the output stage can be used as ESD protection devices. Generally, the output stage has a double protection ring to prevent latching. When designing the ESD structure of the entire chip, pay attention to the following principles: (1) Make the peripheral VDD and VSS lines as wide as possible to reduce the resistance on the lines; (2) Design a voltage clamping structure between VDD and VSS that can provide a direct low-impedance current discharge channel between VDD and VSS when ESD occurs. For circuits with a larger area, it is best to place such a structure around the chip. If possible, placing multiple VDD and VSS PADs on the periphery of the chip can also enhance the overall circuit's anti-ESD capability; (3) The power and ground routing of the peripheral protection structure should be separated from the internal routing as much as possible, and the peripheral ESD protection structure should be designed as uniformly as possible to avoid ESD weak links in the layout design; (4) The design of the ESD protection structure should balance the ESD performance of the circuit, the chip area, and the impact of the protection structure on the circuit characteristics such as input signal integrity, circuit speed, and output drive capability. The tolerance of the process should also be considered to optimize the circuit design; (5) In some actual designed circuits, there is sometimes no direct VDD-VSS voltage clamping protection structure. At this time, the voltage clamping between VDD-VSS and the ESD current discharge mainly use the contact space between the well and the substrate of the entire circuit of the whole chip. Therefore, the contact between the well and the substrate should be increased as much as possible in the peripheral circuit, and the spacing between N+P+ should be consistent. If there is space, it is best to add a VDD-VSS voltage clamp protection structure next to and around the VDD and VSS PADs. This not only enhances the ESD resistance in the VDD-VSS mode, but also enhances the ESD resistance in the I/OI/O mode. Generally, as long as the above principles are followed and the chip area is compromised, the ESD resistance voltage of a general submicron CMOS circuit can reach more than 2500V, which can meet the ESD reliability requirements of commercial civilian circuit design. For deep submicron ultra-large-scale CMOSIn the design of IC ESD structure, conventional ESD protection structure is usually no longer used. Usually, most foundry production lines with deep submicron process have their own peripheral standard ESD structure, with strict standard ESD structure design rules, etc. Designers only need to call their structure, which allows chip designers to focus more on the design of the function and performance of the circuit itself. 4 Conclusion ESD protection design is becoming more and more difficult with the improvement of CMOS process level. ESD protection is no longer just an ESD protection design problem for input or output pins, but an electrostatic protection problem for the entire chip. Corresponding ESD protection circuits need to be established in each I/O circuit in the chip. In addition, the entire chip must be considered as a whole. Using a whole-chip protection structure is a good choice, which can also save the area of ESD components on the I/OPAD.