Questions and Answers on PIC Microcontroller Interrupts

Compared with 51 or other series of microcontrollers, the interrupt mechanism of PIC microcontroller has its own special features. In response to some problems and doubts that some of our beginners have, I would like to make a personal summary here. If there are any inappropriate parts, please correct me.

I will first quote three replies regarding the understanding of PIC interrupts, and then I will give a more detailed summary and explanation of the process of interrupt activity, matters that should be paid attention to, and a doubt.

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JohnFrank: I don't understand something about PIC interrupts.

Borrow the procedure of prawns;

;************************Interrupt service code

btfssINTCON,T0IE; Determine whether it is T0 interrupt

gotoother_int

btfssINTCON,T0IF;it'sthetimeofT0int

gotoother_int

bcfINTCON, T0IF; is T0 interrupt, clear interrupt flag

movlw0x10; the high byte of microseconds plus the high byte of the timing time 256x16 division = 4096 = 0x1000 (0x10)

addwfus+1

gotoend_int

other_int; other interrupt service codes can be added

nop;otherisrcodecanbeadded

;************************************

end_int; Restore the scene

=================

If a new interrupt occurs in the middle of this program

btfssINTCON,T0IF

gotoother_int

bcfINTCON,T0IF

Isn't it possible that the program will fail?

johnfrank:

Thank you for your attention.

I will tell you my understanding and just give you an answer. If there are any inappropriate points, please point them out to me.

The pic mid-range microcontroller series does not have "hardware interrupt priority" (please allow me to say this), which means: when the kernel is processing the current interrupt service A, during this period, any other interrupt can only set its flag bit xxIF to 1, and cannot deprive the current interrupt service of the CPU's occupancy (reflected in the PC pointer cannot be changed by the new interrupt), and must wait until the current interrupt service A is completed, and then, according to the direction of the gotoother_int statement, judge in turn. If the new interrupt processing code is after the interrupt service A (before and after refer to the address sequence of the code in the ROM, the larger the later), the new interrupt processing will be carried out; if the new interrupt service code happens to be before the interrupt service A code that has just been processed, it will be ignored (that is, the program pointer PC will not return to the entry 0004H in the interrupt processing code space), and wait until retfie is executed to return to the main program, and then enter the interrupt entry 0004H again...

The reason why it is said that there is no "hardware interrupt priority level" is that it corresponds to the "software interrupt priority level". The priority level can be set by the order in which the interrupt service code detects the interrupt flag and IE. [page]

Of course, to be precise, this is an order, not a level, haha.

If you understand the interrupt system of 51, I believe you can better understand the interrupt level of PIC:

The situation you mentioned will occur. When a higher priority interrupt comes, the kernel will temporarily stop the current interrupt service, save the current interrupt service scene, execute the higher priority interrupt service, and after the processing is completed, restore the scene and execute the unprocessed interrupt service... Finally, return to the main program.

My explanation is a bit complicated and not very vivid. There may be omissions and errors. Please correct me. I believe that after reading the book carefully, John Frank should be able to form his own correct opinion.

zdtdl: I have something to say~~

Simply put, when the system responds to an interrupt, the GIE bit will be automatically cleared to disable other interrupts. After executing the interrupt return instruction RETFIE, the system automatically sets the GIE bit to 1 to enable interrupts. As long as GIE is not set to 1 in the interrupt program, there will be no repeated interrupts, and the response is determined by the query method. PIC also has interrupt nesting, which can form multi-level nesting, even self-nesting, but the number of nesting levels must not exceed the depth of the hardware stack.

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PIC mid-range microcontroller interrupt summary text

1. The process of interrupting activities

For PIC microcontrollers, an interrupt process generally has the following stages:

In order to make the explanation vivid and intuitive, this article uses some humorous sentences to illustrate:

Interruption request - like a request to buy affordable housing

Interrupt flag -------An application

This interrupt enables xxIE-----leader of this unit

PEIE-------------Director of the Household Registration Office

GIE--------------The head of the bank's credit management department

1. Interrupt request: There are too few houses. My son is getting married and needs to buy a house. However, due to limited resources and financial resources, we cannot sell commercial houses. We have to deal with it as a special case and write an application (interrupt flag IF is set to 1);

2. After reading it, if the leader xxIE of this unit gives you a stamp: (that is, the interrupt enable bit IE=1), then congratulations, this application can be submitted to a higher level department; if not (xxIE=0), then sorry, leave it here first, and we will talk about it after we have studied it. If you are not happy and want to take back the application and tear it up, haha, then IF=0; your dream of purchasing a house is shattered;

3. The xxIE leader will classify these applications according to the household registration. One category is the household registration moved from other places, which will be submitted to the PEIE director of the household registration office for review. If the PEIE director stamps you (PEIE=1), then he will submit the application to the bank's GIE section chief for approval, otherwise it will be kept here for further study or you can come back and tear it up; the other category is the local household registration, which can be submitted directly to the bank's GIE section chief for approval, and then you will take the application to the GIE section chief's office.

4. After the GIE chief stamps the application (GIE=1), you can take the application to the real estate agent to apply for the house (PC pointer=0004H at this time). Because the GIE chief has a lot of things to do, he hangs a sign outside the office door after stamping each time (note that it is one time, not multiple times, because there may be multiple interrupts at the same time, that is, people from other places come to ask the GIE to stamp), saying "Do Not Disturb". He will go to rest until he receives a call from RETFIE or someone calls his mobile phone.

5. The real estate developer is ready to give you the house, but you'd better fill out various procedures first, including a 50,000 yuan deposit, and you have to handle the agreements and contracts yourself. This is called "protecting the scene."

6. The real estate agent starts to work, and then checks who submitted the "application" one by one, so as to arrange the house you reserved for you. This is called "interrupted inquiry".

7. After finding out that it is yours, they will call you to come over, take you to see the house, and give you the key. This is called "interruption processing".

8. After the keys are handed over to you, you have the house, but the application form becomes invalid and the real estate agent destroys it. This is called "clearing the interruption mark".

9. OK, now you can go to the real estate agency and ask for your deposit, ID card, etc. This is called "restoring the scene".

10. Finally, the real estate agent finished the work and asked Miss RETFIE to call the GIE section chief (execute the RETFIE instruction). The GIE section chief then stood up, took down the "Do Not Disturb" sign, and let other people with applications in. Of course, if your work is not done yet, and the GIE section chief's relative calls his cell phone (when you are doing business - processing interrupts, if GIE is set to 1), he will also open the door and take down the "Do Not Disturb" sign, let the relative come in, and stamp it for him. Sorry, he has a relative, so you have to stop your work immediately and wait for the relative to finish his work before you can do your work. This is called "interrupt nesting". Please note that the GIE section chief has 8 relative customers (the depth of the hardware stack is 8 levels).

2. Issues that need attention:

1. Interrupt the protection of the scene (you can refer to the previous post, under the guidance of the moderator xieyubing, there are appropriate examples);

2. The initial power-on reset, power drop reset and reset in other situations all make the global interrupt bit GIE and other interrupt enable bits xxIE = 0;

3. The state of the interrupt flag bit has nothing to do with whether the interrupt source is masked or not, nor has it anything to do with the global interrupt enable bit GIE.

4. When an interrupt source is opened, the interrupt source applies for an interrupt to the CPU through the interrupt flag. Regardless of the reason, as long as the flag IF is set to 1 (it can be forced to 1 by software), an interrupt request will be generated.

5. When the interrupt flag is 1, if the interrupt is masked or disabled, as long as the flag is not cleared, the interrupt request will be dormant, and once the mask is lifted, an interrupt response will be generated immediately. Conversely, if the flag is cleared before the mask/disable condition is lifted, there will be no interrupt request.

6. When the CPU responds to any interrupt, the global interrupt enable bit GIE will be automatically cleared to 0; when the interrupt returns, it will be automatically set to 1. If the GIE bit that has been cleared to 0 is reset by software during interrupt processing, if an interrupt request appears again at this time, interrupt nesting can be formed. That is, when responding to other interrupt requests during the processing of a certain interrupt, interrupt nesting is formed. At this time, the previous interrupt processing process will be suspended and enter the new interrupt processing. When the new interrupt processing is completed, the previous suspended interrupt will continue to be processed. This method can form multi-level nesting, but it cannot exceed the depth of 8 levels of the hardware stack to avoid stack overflow and failure to return normally. [page]

7. If multiple interrupt requests occur simultaneously, the order in which the interrupts are processed depends on the order in which the interrupt sources are checked in the interrupt routine.

8. To prevent interrupt requests from being lost, pay attention to the following two situations: If the interrupt interval of the same interrupt source is greater than the processing time of the interrupt service, the interrupt event may be ignored (reflected in the interrupt service process, the flag bit is set twice in succession). For example, if the interrupt event interval is 30ms, and the interrupt service processing plus the jump judgment time is 50ms, the situation will be as follows:

[Number of interruptions----------1][Number of interruptions----------2][Number of interruptions----------3][Number of interruptions----------4]

[Number of processing times------------------------1][Number of processing times------------------------2][Number of processing times------------------------4]

If IF is cleared at the beginning of interrupt processing, as shown in the figure above, interrupt events 3 and 4 occur twice during processing time 2. In this case, even if IF is cleared before interrupt time 3 occurs, the third interrupt will be lost.

In addition, even if the time interval between interrupts is greater than the time interval between interrupt services, if the instruction to clear the interrupt flag is placed at the end of the interrupt service subroutine, the interrupt request may be lost (i.e., two interrupt flag setting events correspond to only one clearing instruction and one interrupt processing).

9. When performing a table lookup operation, the CPU must be prohibited from responding to interrupts to avoid jumping to an unwanted address when the interrupt returns.

3. A doubt

A question: Some books mention that if you perform a "read-modify-write" operation on the INTCON register, you must clear GIE to 0 in advance, then operate INTCON, and then restore GIE to 1

BCF INTCON, GIE

BSF INTCON,XX

BSF INTCON,GIE

The reason mentioned is: when the CPU is executing an instruction that performs a "read-modify-write" operation on the INTCON register, if an interrupt request happens to occur, the interrupt service routine will be executed twice. This is because when an interrupt request occurs, the GIE register of the INTCON register will be automatically cleared by hardware (masking all interrupts), and the program will enter the interrupt routine entry (0004h). When GIE is cleared, if the CPU is executing a "read-modify-write" instruction on INTCON, the GIE bit will be reset to 1 by the write operation, which will cause the CPU to enter the interrupt service routine twice.

This paragraph of explanation is obscure and difficult to understand. According to the timing of the interruption process (page 8-2 of the PICmicro mid-range MCU series reference manual): In the nth instruction cycle, the CPU detects that the IF flag is 1, then GIE=0 will be automatically set in the n+1 cycle. No instructions will be fetched or executed in this cycle. Then in the n+2 instruction cycle, the 0004h pointer is loaded into the PC pointer. No other instructions will be executed in this cycle. Only the instruction fetch process of 0004H->(PC) is completed. In the n+3th instruction cycle, the CPU executes the instruction code at address 0004h and fetches the instruction code at 0005h at the same time.

Obviously, the author's explanation that "when GIE is cleared to zero, if the CPU is executing a "read-modify-write" instruction on INTCON, the GIE bit will be reset to 1 by the write operation, which will cause the CPU to enter the interrupt service routine twice." has the following problem: the cycle when GIE is automatically cleared by hardware is a no-run cycle, and the CPU does not execute instructions. The next cycle is also a no-run cycle, but it completes the instruction fetch operation of the code at address 0004h. Then the execution operation of the code at address 0004h and the instruction fetch process of the code at address 0005h begin. So there are only two ways to set GIE to 1 after it is automatically cleared by hardware: the RETFIE instruction automatically sets GIE to 1; and the software instruction manually sets GIE to 1. Obviously, if the instruction to manually set GIE to 1 is executed before the flag is cleared to zero, the interrupt nesting mentioned above will occur (assuming that the interrupt is A). If no other interrupts occur and the execution order precedes interrupt A and the flag of interrupt A is cleared to zero, then the nesting of interrupt A is an infinite loop. It is not a problem of executing twice - because when the same interrupt is nested, GIE is always set to 1 by software after it is automatically cleared before IF is cleared, so IF is never cleared and GIE is almost always 1.

The situation described by the author seems to be this: the read, modify and write INTCON instructions are decomposed according to the following process: when reading INTCON, GIE is first 1, an interrupt occurs at this time, GIE is cleared by hardware, and the interrupt service routine begins to execute. Then, before the IF flag is cleared, the other bits of INTCON are modified and written back, and the information that GIE was read as 1 before the interrupt occurs is also written back to GIE. In this way, the CPU is forced to interrupt for the second time. Obviously, this is to break the BSF INTCON, XX instruction into pieces---the instructions that can be completed in one instruction cycle are spanned across multiple instruction cycles; and the instructions of one instruction cycle are broken down by the CPU at different addresses to execute the read, modify and write process.

If this is not the case, then the author's explanation is self-contradictory: "When the CPU is executing an instruction that performs a 'read-modify-write' operation on the INTCON register, if an interrupt request happens to occur" contradicts "When GIE is cleared, this is if the CPU is executing an 'read-modify-write' instruction on the INTCON register."

Anyway, I have some doubts about my understanding here. Please give me some advice, moderator and seniors.