Realizing the Communication between DSP2407A and S3C4480 by Using CPLD

    In modern automotive electronics , there are usually multiple microcontrollers working together in coordination. DSP controllers use Harvard structure and have fast computing speed, so DSP chips are widely used in automotive electronics to control the automotive power system. ARM is a 32-bit microcontroller with rich external expansion interfaces. Therefore, ARM is generally used in automotive electronics to implement large-capacity data storage and human-computer interaction or GPS global positioning system, so data exchange is required between DSP and ARM.

    CPLD (Complex Programmable Logic Device) is a complex user-programmable logic device. Due to the use of hardware programmable technology, it is as convenient to design hardware circuits as to design software. DSP2407A is a microcontroller designed by T1 to meet a wide range of digital motor control applications. S3C4480 is a cost-effective microcontroller designed by Samsung for handheld devices. This design takes Xilinx's XC95108 as an example, and realizes parallel communication between DSP2407A and S3C4480 by opening up two independent SRAM areas (1 byte each) in CPLD. With this communication mode, data transmission is accurate and high-speed, which can basically meet the requirements of real-time communication between DSP2407A and S3C4480 bus interface, thus organically unifying vehicle power control and human-computer interaction.

1 Overall system structure design
    DSP2407A is responsible for collecting all the data of the car, and then sending the data to S3C44B0 through CPLD for data storage and human-computer interaction. Sometimes S3C4480 needs to receive touch screen commands, and the commands are also sent to DSP2407A controller through CPLD to control the action of the entire car. For DSP2407A, it is necessary to respond to the commands sent by S3C44B0 in a timely manner; and for S3C4480, it is necessary to receive the data sent by DSP2407A at any time, so that the real-time communication between the two parties must be very strong. Therefore, in the system design, DSP2407A receives data in interrupt mode, and S3C44BO receives data in query mode.

    In DSP2407A, [DO~D7] is the data line, [A15~A12] is the address line, IS is the I/O space selection pin, and it is low when accessing external memory or I/O space. WE is write enable and RD is read enable. IOPC7 is a general-purpose I/O pin, which is used to determine whether DSP2407A can write data to CPLD. When IOPC7 is low, it means that DSP2407A can write data to CPLD; if it is high, it means that there is data in CPLD, and DSP2407A cannot write data to CPLD. XINT1 is an external interrupt, which is used to notify DSP2407A to prepare to read data in CPLD.

    In CPLD, it is implemented with 1 XC95108. XC95108 has a total of 108 macro units, which has enough space to implement 2 8-bit SRAM areas; it is mainly used to implement data exchange between DSP2407A and S3C44B0, and does not set the status bit of DSP2407A and S3C44B0 read/write control. In S3C44B0, [D0~D7] is the data line, nGCS1 is the chip select signal, and the chip is activated when the memory address is in the address area of ​​the corresponding segment. nWE is the write enable signal, and nOE is the read enable signal. IOPF0 is a general I/O port, used to monitor whether data can be read from the CPLD: when it is high, it means that there is data in the CPLD and the data can be read; when it is low, it means that there is no data in the CPLD to be read. IOPF1 is a general I/O port, used to monitor whether data can be written to the CPLD: when it is high, it means that there is no data in the CPLD and data can be written to the CPLD; when it is low, it means that there is data in the CPLD and S3C44B0 cannot write data to the CPLD. The system structure is shown in Figure 1.

2 CPLD design
    uses Xilinx ISE8.1 as the design tool, and uses the internationally common VHDL language to write the source program.

2.1 8-bit data is transferred from DSP to ARM
    When [A15~A12] is 1100, DSP2407A starts to write data to CPLD, and sets dspsign_write and armsign_read to 1; it means that there is already data in CPLD, notifying S3C4480 that it can read data and DSP2407A that it cannot write data to CPLD temporarily; at the same time, the data is written to latch sraml.

    When ARM sends a read data signal, it starts to read data from sraml, and sets dspsign_write and armsign_read to 0, it means that there is no data in CPLD, and DSP2407A can rewrite data to CPLD.

2.2 8-bit data is transferred from 83CA480 to DSP2407A
    When S3C4480 writes data to CPLD, it writes the data to latch sram2 and sets dsp_int to 0, notifying DSP2407A to generate an external interrupt and fetch data from CPLD; armsign_write is set to 0, indicating that there is already data in CPLD and S3C4480 can no longer write data to CPLD. [page]

    When [A15～12] is 1101, DSP2407A sends a read signal to CPLD, data is transferred from latch sram2 to DSP2407A, and dsp_int is set to 1 and armsign_write is set to 1, indicating that the data has been read by DSP2407A and S3C4480 can continue to write data to CPLD.

3. Communication software design between S3C4480 and DSP2407A
    In this program, DSP2407A uses interrupt mode to receive data, and S3C4480 uses query port mode to receive data.
(1) DSP2407A program

   

(2) S3C44B0 program