Three clock signals of MSP430 microcontroller

(1) MCLK System master clock. In addition to the CPU operation using this clock signal, peripheral modules can also use it. MCLK can select any clock signal generated by an oscillator and divide it by 1, 2, 4, or 8 as its signal source.

(2) SMCLK System sub-clock. It can be used by peripheral modules and can be divided by registers of each module before use. SMCLK can select any clock signal generated by an oscillator and divide it by 1, 2, 4, or 8 as its signal source.

(3) ACLK auxiliary clock. It can be used by peripheral modules, and the frequency division can be realized through the registers of each module before use. ACLK can only be divided by 1, 2, 4, 8 by LFXT1 as its signal source. At the end of PUC, the signal source of MCLK and SMCLK is DCO, and the oscillation frequency of DCO is about 800kHz (see the relevant manual for details). The signal source of ACLK is LFXT1.

The MSP430 contains a crystal oscillator failure monitoring circuit to monitor the clock signals output by LFXT1 (working in high-frequency mode) and XT2. When the clock signal is lost for about 50μs, the monitoring circuit captures the oscillator failure. If the MCLK signal comes from LFXT1 or XT2, the MSP430 automatically switches the MCLK signal source to DCO, which ensures that the program continues to run. The MSP430 does not monitor the LFXT1 working in low-frequency mode.