Data acquisition system of logic control module based on FPGA

In the image processing system, the video signal collected by the camera is first converted into an A/D signal, and the analog image signal is converted into a digital signal, which is provided to the back-end processing system for image processing. The video image acquisition system is a front-end subsystem of multimedia information processing, video surveillance and other systems, and is an indispensable part of the video processing system. The traditional video acquisition system generally has complex circuits, high costs, and it is difficult to meet the real-time requirements. The video camera + video decoder + FPGA mode can simplify the complexity of the circuit, in which the video decoder performs AD conversion on the signal collected by the camera, and the FPGA controls the sampling of the signal. The FPGA has a high clock frequency and a small time delay, which can meet the real-time requirements. Based on the above advantages, this paper adopts some structures to realize video image acquisition.

1 Video Decoder SAA7113H
SAA7113H is an enhanced video input processor of Philips Company. It has a series of registers inside, and the reading and writing of the registers are completed through the I2C bus. It includes a dual-channel analog preprocessing circuit, programmable static gain and automatic gain control circuit, clock generation circuit, digital multi-standard decoding circuit, brightness, contrast, saturation control circuit and I2C bus control circuit. SAA7113H needs an external 24.576 MHz crystal, and the internal phase-locked loop PLL can output a 27 MHz clock. It automatically detects 50 Hz and 60 Hz field frequencies and can automatically switch between PAL and NTSC. It has 4 analog video signal inputs, and the conversion of 4 signals can be achieved through different configurations of the internal registers; the input can be 4 CVBS or 2 Y/C signals or 1 Y/C signal and 2 CVBS, and the output is a VPO data bus (8-bit) in the standard ITU656 YUV4:2:2 format. The analog and digital parts of SAA7113H use +3.3V, and the digital I/O interface is compatible with +5V.

2 System overall plan and working principle
The system uses EP2C20Q240C8 in the CycloneⅡ series of ALTEra as the hardware platform of the system. The chip has 18752 LEs, 26 multipliers and 4 phase-locked loops. The video decoding chip uses Philips' SAA7113H. The system mainly consists of SAA7113H image acquisition interface module, I2C bus configuration module, control module, pixel storage module, format conversion module and display interface module. VHDL language is used in the design for programming and debugging under QUARTusⅡ. The basic structure of the system is shown in Figure 1.

3 Introduction to the functions of the main modules
3.1 SAA7113H image acquisition interface module
This module is responsible for the acquisition of video images and converts analog video signals into digital video signals to prepare for the subsequent video processing. This module is connected to the VPO data bus, RTS0, RTS1, and LLC of SAA7113H. RTS0 and RTS1 are configured as line synchronization and field synchronization signals respectively. Only when these two signals are valid at the same time, the output data is valid image data, otherwise it is a blanking signal. The valid video signal is divided into odd fields and even fields, with a total of 576 lines of valid data, of which the odd field valid data is 23 to 310 lines, the even field valid data is 336 to 623 lines, and the rest
are vertical control signals.
The frequency of the VP0 bus output data of SAA7113H is 27 MHz, and 1 Byte of valid data is output on the rising edge of each LLC. Each pixel of the standard ITU YUV 4:2:2 format video signal has its own brightness component Y, and every two adjacent pixels share a pair of color difference data Cb and Cr. When storing pixel data, it can be considered that every two consecutive bytes represent a pixel. When format conversion or other processing is required, the data of two adjacent pixels should be extracted at a time for corresponding processing. Among them, each line has 864 data sampling points, 720 of which are valid data, and 144 data during blanking. In a complete frame of image data, the blanking EAV of the first field is FF 00 00 BX, and the blanking SAV of the first field is FF 00 00 AX; the valid data SAV of the first field is FF 00 00 8X, and the valid data EAV is FF 00 00 9X, and the same applies to other fields. The SAV of the valid data stage of the odd field is "FF 00 00 80", and the SAV of the valid data stage of the even field is "FF 00 00 C7". 8 bits of data are read at the rising edge of each clock. When the start mark FF 00 00 XY of a line of data is detected, the SAV or EAV signal is detected, and the H, F, and V signals are extracted. Then it starts decoding the image data, judging whether the data is Y, Cb or Cr according to the information of the 8-bit data, and thus obtaining the Y, Cb, and Cr components.
3.2 I2C bus configuration module
This module configures SAA7113H through the I2C bus protocol, with a clock frequency of 20 kHz. The SAA7113H configuration is completed through this module. The configuration module is shown in Figure 2.

Among them, the inICio_conf signal indicates the start of configuration of SAA7113H, and the high level is valid. clk is the clock signal. reset is the external reset signal with a high level valid. SCL and SDA are SAA7113H configuration signals. CONFIGURACION_OK means that after the decoding chip is configured, a control signal is output to the control module to start data acquisition.
The register address of SAA7113H starts from 00H, and only 01H~05H front-end input configuration part, 06H~13H, 15H~17H decoding part, 40H~60H conventional separation data part, these are readable and writable, and the rest are reserved addresses or read-only registers. The register data to be configured is stored in the lookup table con_data, and count is used to indicate which register is currently configured. The registers are written one by one during configuration. [page]

According to the timing of I2C bus data transmission, the state machine of the bus controller is divided into idle state, start state, data transmission state, response state and stop state. The Idle state indicates the idle state of the bus, SCL and SDA are both high, and if clk=1, it enters the Start state. The Start state indicates that the bus is started. At this time, SCL is kept at a high level and SDA is changed from a high level to a low level to start data transmission. In the Data_trans state, 1 Byte of data is transmitted at a time. In this state, the transmission process of 1 Byte of data is to change the clock line to a low level and then put the data on the data line SDA. Then change the clock line to a high level to allow the receiver to receive the data. After transmitting 1 Byte, it enters Hold. The Hold state is used to indicate the response stage, which mainly generates a clock pulse to allow the receiver to generate a response signal for 1 Byte of data. In this state, it is judged whether the continuous transmission of this data is completed. If the transmission is not completed, continue to the Start state for the next data transmission and count-1. The Stop state indicates the end of data transmission. During the high level of SCL, SDA is changed from low to high. Then a configuration completion signal is output. The register configuration state machine is shown in Figure 3.

3.3 Control module
The control module consists of control_enable module and control_interface module, which are mainly responsible for the synchronization and enabling of image acquisition module and display interface module. When the decoding chip is configured, the enable signal is input from CONFIGURACION_OK to start the module, and the image acquisition module and display interface module are started through href and odd signals. href=1 means that SAA7113H transmits pixel data through VPO; odd=1 means odd field, and odd=0 means even field.
3.4 Pixel storage module
One frame of the image is 720×625, and the effective pixels 640×576 are extracted and stored in SDRAM, and then 480 lines of data are read out for format conversion and display.
Since each unit of SDRAM is 16 bits, one Y and one Cb or Cr are stored in one address space, that is, two clock cycles generate one address. SDRAM has 4-port mode, 2 for writing data in FIFO to SDRAM, 2 for reading data from FIFO, different clocks are used for reading and writing, the write clock uses 27MHz of the decoding chip, and the decryption clock uses 25MHz of VGA. Since the read and write speed of SDRAM is 50 MHz, the clock frequency is different and cannot be written directly, so a FIFO is needed to temporarily store the data and then write it to SDRAM.
The key issue here is the conversion from interlaced scanning to progressive scanning. SAA7113H outputs the odd field first and then the even field in sequence, that is, interlaced output, while VGA display is progressive display, so deinterlacing operation is required. The control of the read and write address of SDRAM can effectively solve the problem of conversion from interlaced to progressive. Writing data into SDRAM means writing interlaced data into the address space of 0-640×576 of SDRAM, where 640×23-640×310 is valid data of odd fields 1, 3, 5, ..., and 640×336-640×623 is valid data of even fields 2, 4, 6, .... The two fields of data are read out through different FIFOs respectively. When converting the format, the data in the two FIFOs are read crosswise, so that the data read out is 1, 2, 3, 4, ... progressive data.
3.5 Format conversion module
To display the image collected by the camera on the display, the data format conversion is required to convert the YUV format data into RGB format data. Two adjacent pixels in YUV 4:2:2 format share a pair of Cb and Cr components, so when performing format conversion, deinterleaving must be done first, that is, extract two adjacent pixel data from FIFO at a time, reuse Cb and Cr once each, so that YUV becomes 4:4:4 format, and then perform format conversion. The converted data is stored in reg_RGB, and the data in these two registers are read crosswise during VGA display. The conversion formula is as follows

Since floating-point operations are difficult to perform in FPGA, the coefficients in formula (1) can be converted into integers for operation. The method of amplifying each coefficient by 1 024 times is adopted to obtain r, g, and b, and then divide them by 1 024. The amplified formula is

According to the above formula, r, g, and b are obtained. Then the results are all shifted right by 10 bits to complete the division operation and obtain the RGB value. Since r, g, and b are all 8 bits, the value range is 0 to 255, and the operation process is more likely to generate negative numbers and positive numbers exceeding 255, so the operation result needs to set negative numbers to 0 and positive numbers exceeding 255 to 255. Although this method will introduce errors, it will not have a significant impact on the display effect of the final image.
3.6 Display interface module
Interface_vga is responsible for displaying the image and reading the converted data from the reg_RGB register. A conversion circuit is responsible for switching between the two registers to read the two pixels. The display interface module sends r, g, b, hsync, and vsync to the encoding chip THS8134 and displays them through VGA. hsync and vsync are the line and field synchronization signals respectively. In the simulation, the CycloneⅡEP2C20Q240C8 chip is selected and QUARTusⅡ8.0 is used for synthesis and simulation. Figure 4 is a simulation of the display interface module. It can be seen from the simulation results that the line synchronization and field synchronization meet the timing requirements.

4 Conclusion
An embedded image acquisition system based on CycloneII series FPGA and video signal processing chip SAA7113H is implemented. The system has a simple structure, stable system, low power consumption, low cost, fast speed and convenient interface, which can meet the needs of video surveillance systems. Using FPGA as the acquisition control part in the image acquisition system can improve the system processing speed and the flexibility and adaptability of the system. For different video image signals, signal acquisition can be achieved by slightly modifying the control logic in the FPGA.