Design and implementation of multi-DSP boot scheme for link port based on CPCI bus

Preface

Digital signal processor (DSP) is a microprocessor with a special structure. It is specially designed to implement various algorithms for digital signal processing, so it has special hardware structure. TS201 is a high-speed DSP in the TigerSHARC series of ADI that integrates fixed-point and floating-point computing functions. This processor is widely used in the video, communication market and defense military equipment, and is suitable for the application field of real-time processing of large amounts of data.

The loading method of the TigerSHARC series DSP boot program is very flexible and can be flexibly selected according to the actual system requirements. A radar signal processor adopts a 6U board shape, and the CPCI bus adopts the European card size standard. Data communication with the host is carried out through the CPCI bus. For the hardware system of the signal processor, this paper proposes a boot scheme that uses the CPCI bus to transmit the boot code to the board card, and then relies on the FPGA to boot the DSP through the link port.

1 ADSP-TS201 boot mode

DSP booting is the process of loading algorithm program code from DSP external memory when DSP system is reset. TS201 supports two boot modes: Master Boot mode and Save Boot mode.

In the master boot mode, TS201 acts as the active party, using the external port to output the address, read the boot mode selection and other control signals to load the code from the EPROM or FLASH. In the slave boot mode, TS201 acts as the passive party, does not output control signals to the outside, and the external host or other device transmits the code to be loaded to the host or link port of TS201. TS201 only starts several DMA channels and executes the loading core received by the first DMA.

In addition, FS201 can also select a "non-boot" mode, or use TS201's (emulator) USB-ICE to load the program. This method can directly load the program into TS201's internal RAM or external RAM. The DSP runs the program directly from the RAM, which is often used in the DSP debugging process.

By setting the pins of TS201, the boot process of DSP can be set to master boot mode or slave boot mode. During DSP reset, if the pin is low, the master boot mode is selected, and DSP loads the program from the external EPROM or FLASH; if the pin is high, it enters the slave boot mode, and DSP is in idle state, waiting for the host or link port to load the program. Both boot modes have the same loading process, and the specific steps are as follows:

(1) TS201 automatically starts a DMA and automatically transfers 256 words (32 bits) to the internal memory at addresses 0x00 to 0xFF.

(2) TS201 executes the above 256-word instructions (loading core), and the loading core starts other DMAs to load subsequent instructions and data into internal and/or external memory.

(3) Load the core self-overlay and execute the DSP algorithm program.

The boot scheme of this system adopts the slave boot mode, which transfers the code from the host to the FPGA through the CPCI bus, and then uses the FPGA to start the DSP through the link port.

2 Guidance Design Scheme of a Radar Signal Processor

Based on a radar signal processor hardware processing platform, a multi-DSP guided design scheme as shown in Figure 1 is adopted.

The algorithm program codes (.LDR files) of the four DSPs are transferred to the FPGA through the host computer software, and the FPGA loads the program to the DSPA through the link port with the DSPA. After the DSPA is loaded successfully, it guides DSPB, DSPC, and DSPD to start respectively.

The advantages of loading DSP in this way are: JTAG emulator is not required when debugging DSP; at the same time, when DSP starts itself, FLASH or E2PROM is not required to store program code. There is no limit on the size of DSP program, which also saves circuit board space and hardware design complexity.

The difficulties of loading DSP in this way are: correct data transmission between CPCI bus and FPGA and communication between FPGA and TS201 link port. These two difficulties have been solved in actual projects. The CPCI bus and FPGA interface can use PLX9656 chip to complete data transmission, so the design of this loading mode is feasible.

2.1 Design ideas of automatic boot program

In order to design the loading (automatic boot) program, we must first understand the software design process of ADSP-TS201, the flow chart of which is shown in Figure 2.

The link description file (.LDF) defines the memory configuration of the entire system and the specific storage location of data and code in the program. The loading core file (.DEX) refers to the loading boot core program, which is used to synthesize the executable file (.DXE) compiled successfully by the user project into a link port loading mode output file (.LDR). The loading output file is used to define how the internal and external memory of TS201 is initialized during the loading process.

In the ldr subdirectory of the VisualDSP++ installation directory, ADI provides standard loading core files and corresponding source programs (.ASM) and link description files. Generally, you can directly use the provided standard loading core files or simply modify the corresponding source programs, recompile and link the generated loading core files. The loading file is generated by the boot loader (elfloader) by changing the executable file to a certain format and attaching the loading core file to the starting position.

Since TS201 has three boot modes (not considering non-boot mode), ADI provides three different loading and files accordingly, namely: TS201_prom.dxe, TS201_li-nk.dxe, TS201_host.dxe. The core ideas and functions of the three programs are exactly the same, but there are slight differences in the specific code implementation due to the different loading ports and methods used. Since this system uses the link port to start, and different link ports are used to start DSPA, DSPB, DSPC, and DSPD, the link port loading core file is used, and the loading core file needs to be slightly modified to meet the needs of starting with different link ports.

2.2 Reset boot design process of this signal processor

As shown in Figure 1, the programs to be run by the four DSPs are finally read by the host computer and transmitted to the FPGA through the CPCI bus. The four DSPs are in link port boot mode. After the DSP is reset, DSPA loads the program from the FPGA. After DSPA is loaded, DSPB, DSPC, and DSPD are loaded through the link port respectively. After loading, the four DSPs execute their respective programs normally.

Combining the analysis of the above parts, it can be seen that to achieve the correct guidance of the four DSPs in the signal processor, the required work consists of the following steps:

(1) The program to be executed by DSPB (DSPB.dxe) is combined with the link port loader core program to generate the DSPB loading file (DSPB_bin.ldr). It should be noted that the link port loader core program cannot directly use the provided standard link port loader program. The LINK constant in the provided link port loader core file (TS201_link.asm) must be changed to 1 (#define LINK 1), that is, DSPB is guided by link port 1.

(2) Similar to (1), generate the DSPC loading file (DSPC_bin.ldr), except that the LINK constant in the link port loading core file (TS201_link.asm) needs to be changed to 2 (#define LINK 2), that is, DSPC is booted by link port 2. Similarly, DSPD is loaded by link port 2, and the DSPD loading file (DSPD_bin.ldr) is also generated.

(3) Since DSPA needs to use the link port to guide the program of DSPB, DSPC, and DSPD, when programming DSPA, it is necessary to add the boot program of all the following ADSPTS201 at the beginning of the program. The program of each ADSP-TS201 consists of boot code and user program, so when DSPA transmits the program to other DSPs, it will transmit the data of the complete .1dr file. [page]