Design of Enhanced Parallel Port EPP and DSP Interface

Using computers for data acquisition and control has always been a hot topic of research. Most data acquisition and control systems are in the form of plug-in cards; however, for increasingly popular laptops, since there is no expansion slot, they cannot be directly made into a plug-in card. Therefore, it is necessary to make full use of the peripheral interfaces provided by the laptop, such as parallel ports and serial ports. Due to the limitation of serial port speed, for data acquisition and control systems with relatively high speeds, the parallel port of the computer is often used. In recent years, many domestic companies have been working on using the enhanced parallel port (EPP) to communicate with the outside world, but most of them are communicating and controlling some simple peripheral circuits (such as FIFO, A/D converter), and few people involve communication with DSP. The interface between the parallel port and ADSP2181 designed by us provides a way to communicate with complex peripheral circuits.

1. EPP parallel port

The most common computer parallel port mode is SPP mode (standard parallel port). In this mode, data transmission is unidirectional, and the status line cannot be used to complete data input. Therefore, it takes several I/O read cycles to read a piece of data, so the transmission speed cannot be very high, and can only reach 150KB/s. Its peripheral design circuit is not simpler than EPP, so SPP is rarely used in data acquisition and control systems.

In 1992, Intel, Xicom and Zenith jointly developed the EPP1.7 standard, and revised and improved it in the following years. As for the EPP standard, there are mainly two standards, EPP1.7 and EPP1.9; for users, there is no mismatch between them in specific applications.

The EPP protocol is compatible with the standard parallel port and can complete bidirectional data transmission. It provides four data transmission cycles: data read cycle, data write cycle, address read cycle, and address write cycle. The data cycle is generally used for data transmission between the host and the peripheral; the address cycle is generally used to transmit information such as address, channel, command and control. In actual operation, there is not much difference between the two. The address cycle can almost be seen as another data cycle. The only difference will be explained later.

Table 1 gives the definition and description of the signals of each pin in the EPP protocol.

Table 1 Definition and description of each pin in the EPP protocol

Figure 1 is a timing diagram of the EPP data read cycle. The read operation is completed within one I/O cycle. This means that the data transmission rate using EPP can reach 500KB to 2MB/s. Since Nwait is an interlocked handshake signal, the data transmission is carried out by the slowest device of the interface, which can be the host or the peripheral. Therefore, the design of the peripheral circuit is more flexible. [page]

The EPP mode is set in the BIOS. The main things that need to be set are the base address and the interrupt number. It is best to set the base address to 378H or 278H, rather than 3BCH, because the port after 3BFH may be occupied by other devices. EPP has a total of 8 I/O address ports (assuming the base address is 378H); 378H is the data port of SPP; 379H is the status port of SPP; 37AH is the control port; 37BH is the address read and write port; 37HC is the data read and write port; 37DH~37FH can be defined by the user, mainly used as 16-bit and 32-bit I/O data read and write auxiliary ports. By reading and writing the I/O of the port base address + 4, the data read and write cycle of EPP can be generated, and by reading and writing the I/O of the base address + 3, the address read and write cycle of EPP can be generated. The main difference between the address read and write cycle and the data read and write cycle is that the data read and write can do 32-bit and 16-bit I/O read and write, while the address read and write cycle can only do 8-bit I/O read and write (mainly because it has no auxiliary port). In C language, the port read and write functions outportb(), inportb(), outport(), and inport() can be used to implement EPP read and write operations, and the corresponding control signals are automatically generated by the computer.

2. IDMA interface of ADSP2181

ADSP2181 is a type of ADSP21XX fixed-point DSP series manufactured by AD. Its instruction cycle is 30ns, which is sufficient for real-time signal processing. It has a 16MB program storage area (PM) and a 16MB data storage area (DM). The peripheral interface can access the storage area through IDMA and I/O. The biggest advantage of its IDMA operation is that the read and write operations of IDMA do not affect the operation of the ADSP2181 program. However, it should be noted that ADSP2181 and peripherals cannot read and write the same storage area at the same time, otherwise, data disorder will occur.

The IDMA port mainly has the following signal lines: nIRD (input, read enable), nIWR (input, write enable), nIS (input, IDMA enable), IAL (input, address latch enable), IDA0~15 (address/data multiplexing line), and nIACK (output, DSP response signal).

The initial address and storage area type of IDAM reading and writing are controlled by a special register inside ADSP2181. Each time a read or write is performed, the initial address is automatically increased by 1. This register can be set by ADSP2181 or by an external circuit through IDMA operation.

The timing diagram of the IDMA read cycle is shown in Figure 2. The timing diagram of the IDMA write cycle is shown in Figure 3. It should be noted that in the IDMA read cycle, nIWR is high and IAL is low, and in the IDMA write cycle timing, nIRD is high and IAL is low.

3. Interface circuit and overall design considerations

Figure 4 is the interface circuit block diagram we designed. The parallel port control lines include Ndatastb, Naddstb, and Ninit; the DSP control lines include nIS, nWRITE, nREAD, and IAL. [page]

Programmable logic devices are the core components of the circuit. Since the parallel port can only perform 8-bit read and write operations, and ADSP2181 is a 16-bit bus, the combinational logic must be designed for communication. If discrete components are used, the circuit is more complicated and troublesome to debug. After the circuit is fixed, it is impossible to communicate in other ways. With the programmable logic device EPLD, only the logic of the device and the definition of the external pins need to be modified to implement other transmission protocols, such as ECP or other parallel port communications, and debugging is also more convenient.

The programmable logic device we selected is the EPM7128S series from Altera. It has 2500 available gates, 128 macro cells, and 2 global clocks, and can complete the logic design of EPP and ECP circuits. It also supports online programming, and the program can be downloaded very conveniently. The device is programmed with the MAXPLUS II series software, which supports multiple design files such as graphics and languages.

Since programmable devices are used, the circuit can also use the ECP protocol. The ECP protocol supports DMA transmission. The most important thing is that it can save a lot of system resources when transmitting large amounts of data; but there is no significant improvement in transmission speed. This protocol is much more complicated to design than the EPP protocol and requires the development of corresponding hardware drivers. Therefore, in the circuit we designed, the EPP protocol is still used to implement it. 4. Test of EPP parallel port transmission speed

The reading and writing programs are written in VxD. VxD (Virtual Device Driver) is a program used to extend the functions of the Windows operating system. It is also a 32-bit executable program that manages system resources such as hardware devices or installed software, and allows several applications to use these resources at the same time. Windows allows Windows-based applications to implement multitasking by using VxD. VxD handles interrupts in the connection work with Windows and performs I/O operations for specific applications without affecting the execution of other applications. Because the device receives interrupts in the work, and performs I/O operations for specific applications without affecting the execution of other applications.

The test results are listed in Table 2.

Table 2 Comparison of reading rates of various methods

Method 1: Read by bytes in VxD programming;

Method 2: Read by word in VxD programming;

Method 3: Read as double words in VxD programming;

Method 4: Use the inport() function of C language to read and write.

Since we only care about the reading rate from DSP, we can see from Table 2 that the rate can reach 1050KB/s, which basically meets our requirements. For programs written in C language to operate parallel ports, nested assembly can be used to increase the transmission speed.

Summarize

Using EPP protocol to design the communication between computer and peripherals is a novel design method. Using programmable devices to design control logic when designing circuits will be a trend in electronic design, which will greatly improve the expandability and flexibility of circuits.