LVDS Receive

BIT_Wang

LVDS Receive [Copy link]

 I am using Cyclone V FPGA to receive 8-channel differential data, 12bit, 600M data rate. The data received by LVDS_RX core is incorrect. The 8-channel data is not synchronized. Can anyone tell me how to synchronize the 8-channel differential data? Otherwise, the data I decode will never be correct.

BIT_Wang

PS: The Xilinx FPGA routine I read uses iodelay to control the delay of each channel

chenzhufly

Look at the simulation results first, before simulation and after simulation

yupc123

First, make sure your PCB is ok, then the timing analysis should be correct, so please ask more detailed questions.

BIT_Wang

Supplement: I designed an FPGA processing board to drive an image sensor. The sensor sends 8 pairs of LVDS data signals, which I receive with FPGA. The PCB design strictly specifies the equal length of the differential lines, and there is no problem with the PCB board. The sensor manual states that the 8 pairs of LVDS signals are not synchronized, and actual reception requires alignment operations (bit alignment, word alignment, channel alignment). The development board corresponding to the sensor is from Xilinx, and the given bit alignment routine uses iodelay to calculate the delay of each pair of differentials for alignment. I am currently using Altera's FPGA, and I have not found a similar function. The 8 pairs of LVDS data received are sometimes correct and sometimes messy, so I would like to ask how to synchronize the 8 pairs of LVDS signals when receiving using Altera's FPGA.

yupc123

BIT_Wang posted on 2018-11-15 14:38 Supplement: I designed an FPGA processing board to drive an image sensor. The sensor sends 8 pairs of LVDS data signals. I use FPGA to receive them. The difference in PCB design...

I have never seen iodelay in Altera, but I have also encountered your situation. I usually solve it through timing analysis. You can't, there is a simple method, put the main signals into the logic analysis, collect waveforms in real time, and Quartus will automatically add timing constraints for you, and sometimes it can succeed. Finally, I wish you success! !

BIT_Wang

yupc123 posted on 2018-11-16 15:16 I have never seen iodelay in Altera, but I have also encountered your situation. I usually solve it through timing analysis. You don't have a...

May I ask how you solved it specifically? I don't quite understand~