introduction
Sound card technology is one of the key technologies of multimedia computer technology. Its emergence makes computers more expressive. At present, the sound quality of embedded systems is relatively poor due to the simple structure and low sampling rate of the recording and playback chips used, which is far from meeting people's requirements for high-end embedded systems for life and learning. If sound card technology can be applied to embedded systems, the sound quality of the entire system will surely rise to a new level due to the powerful functions of the sound card. Through analysis, the interface principle of WSS (Windows Sound System) compatible sound card and PC ISA bus, we apply the sound effect chip CS4235 in it to the embedded system based on DSP. The reason for not using the ready-made sound card but using the sound effect chip on it is that it is more flexible and convenient to design, and the corresponding functions can be added or deleted according to the needs of the system; the reason for not using the MCS51 series but using DSP is that the sound card operation requires too many system resources, and MCS51 does not have this ability, otherwise the hardware interface circuit will be quite complicated.
1 CS4235 Principle and Structure
1.1 How Sound Cards Work
Figure 1 shows the basic working principle of a sound card: the host sends the digitized sound signal to the digital-to-analog converter (D/A) in PCM format through the bus, which converts the digital signal into an analog audio signal; at the same time, the input signal from the microphone or CD can be converted into a digital signal through the analog-to-digital converter (A/D) and sent to the computer for various processing.
1.2 CS4235 Functional Structure
WSS is an audio subsystem standard defined by multimedia extensions in the Windows environment proposed by Microsoft to unify the sound card standard and ultimately provide convenience for applications. It includes hardware platform and software interface [1]. CS4235 is a sound card core chip that adapts to WSS and provides an ISA bus interface. Except for sound acquisition and playback, all other controls rely on the host; it takes up more host time, but the cost is relatively low. The functional block diagram of CS4235 is shown in Figure 2. As can be seen from Figure 2, CS4235 is a complete audio subsystem integrated circuit that provides 16-bit stereo ADC and DAC, on-chip reconfigurable digital filters, analog and digital mixers with programmable gain and attenuation values, optional serial interfaces, and full-duplex channels with simultaneous recording and playback capabilities. For the documentation of CS4235, see Reference [2].
Due to space limitations, the analog hardware of CS4235 is not introduced here, but the digital hardware interface between CS4235 and DSP is mainly studied. Since
TMS320F206
(F206 for short) is a low-cost, high-performance 16-bit fixed-point digital signal processor (DSP), it has a very high cost-performance ratio and has become an ideal substitute for high-end single-chip microcomputers. It has been widely used in the fields of communication, voice processing, military, instrumentation, image processing, etc. [3], so F206 is selected as DSP in the system. The 8-bit parallel interface provided by CS4235 is compatible with the ISA bus. Is it also compatible with the external expansion bus of DSP? Table 1 lists the signal pins and brief descriptions of the CS4235 and ISA bus interfaces, and also lists the corresponding pins of F206. As can be seen from Table 1, in order to realize the direct operation of DSP on CS4235, the DSP system must provide the above-mentioned ISA bus signals. DSP chips generally provide data signal lines, address signal lines, I/O read/write signal lines, and READY signal lines, and also have multiple interrupt input pins; but they do not directly have DMA function pins, which brings inconvenience to the interface between DSP and CS4235, and is also the main problem to be solved in this paper.
Table 1 Signal pins of CS4235 and ISA bus interface
Signal pin | Brief description | DSP (F206) corresponding pins |
SD<7:0> | Bidirectional system data bus | D<7:0> |
SA<11:0> | System address bus | A<11:0> |
IOR | I/O Read Command | Decoding IS and RD yields IQW=IS+WR |
IOW | I/O write command | none |
AEN | Address enable signal | READY |
IOCHRDY | I/O channel ready | INT2 (In actual application, only one interrupt line needs to be selected to connect to DSP) |
IRQ |
Interrupt request signal: IRQA=IRQ5, IRQB=IRQ7 IRQC=IRQ9, IRQC=IRQ11, IRQD=IRQ11
IRQE=IRQ12, IRQF=IRQ15, IRQG=IRQ10 |
none |
DRQ |
DMA request signal: DRQA=DRQ0
DRQB=DRQ1 DRQC=DRQ3 |
none |
DACK |
DMA response signal: DACKA=DACK0 DACK1=DAC, DACKC=DACK3 | RS |
RESET | Sound card reset signal |
2 Hardware interface between DSP and CS4235
2.1 F206 Direct Memory Access Using HOLD Operation
The key to F206 realizing DMA function is that this type of chip provides two signal pins: HOLD/INT1 and. The HOLD operation process controlled by these two signals is as follows. [page]
①. An external device can drive this pin to a low level to request control of the external bus. If the HOLD/INT1 interrupt line is enabled, this will trigger an interrupt.
②, in response to an interrupt, the software logic can cause the processor to send a response signal, indicating that it will give up control of its external bus. According to, the external address signal (A15~A0), data signal (D15~D0) and memory control signal () are set to a high impedance state.
From ① and ②, it can be seen that the HOLD operation of F206 allows direct memory access to external programs, data, and I/O space, but this function is implemented in the INT1 interrupt program, so the interrupt line INT1 should be sensitive to both falling and rising edges. When F206 detects a falling edge, it completes the current instruction being executed, and then forces the program control to the interrupt service subroutine, which executes the IDLE instruction. According to IDLE, it becomes valid and the external bus is set to a high-impedance state. Only after detecting a rising edge on the HOLD/INT1 pin, the CPU exits the IDLE state, becomes invalid, and returns the external bus to a normal state.
From the above analysis, we can see the difference between the DMA operation of F206 and the DMA operation in PC. In PC, after the CPU receives the DMA request signal, it forces the CPU to put its address, data and some control pins in three states after the current bus cycle ends, thereby giving up the control of the bus and giving a DMA response signal; after the DMA operation is completed and the DMA request signal is invalid, the CPU resumes control of the system bus. In C2XX, the DMA request signal will cause F206 to interrupt, and a software instruction is issued in the interrupt program to make the signal pins of F206 in three states, and also give a DMA response signal; after the DMA operation is completed, but F206 detects that the DMA request signal is invalid, although the bus returns to the normal state, F206 is still in the interrupt program. From the above analysis, we can see that although the interrupt needs to protect the breakpoint and the scene, making the DMA processing speed of F206 much lower than that of PC, after all, F206 also implements DMA operation, so it can use the DMA controller 8237 to realize DMA operation access to the sound card.
2.2 Interface circuit between DSP and DMA controller 8237
8237 is a high-performance programmable DMA controller chip that can be easily connected to the CPU to achieve direct data exchange between external devices and memory. Its internal structure and pin signals can be found in reference [4]. The controller can provide various types of control features through programming to optimize system performance and increase data throughput. The maximum data transmission rate can reach 1.6 MB/s. Figure 3 shows the main circuit of the interface between F206 and 8237, in which the DMA request signal HRQ sent by 8237 to DSP to control the bus is sent to the HOLD/INT1 pin of DSP after being decoded by GAL16V8; similarly, the DMA response signal of DSP is also decoded by GAL16V8 and sent back to the HLDA pin of 8237. The function of the address latch 74LS573 is to latch the high 8-bit address A8~15 output by 8237 through data lines D0~7 during the DMA service cycle. Since DSP does not directly provide the , , and signals, these signals can only be obtained by GAL16V8 decoding.
The circuit shown in Figure 3 provides 4 channels of peripheral request DMA service signals, and the 8237 directly has an AEN pin, which meets all the requirements in Table 1, so that the interface between DSP and sound card can be correctly implemented. In actual work, we set DREQ1 and DACK1 of 8237 as the playback channel of the sound card according to the use of the sound card in the PC, and DREQ3 and DACK3 of 8237 as the acquisition channel of the sound card. The interrupt request signal IRQ7 of the sound card is reversed by GAL16V8 and connected to the pin of DSP.
2.3 System working principle and timing
The DMA operation process of the DSP system shown in Figure 3 on the sound card can be described by Figure 4, and the working sequence is shown in Figure 5. Now, in combination with Figures 4 and 5, the system working principle and operation sequence are explained as follows:
① CS4235 sends a DMA request signal DREQ to the DMA controller 8237;
② 8237 sends a bus request signal HRQ to DSP;
③ After the DSP pin detects the falling edge, it enters the INT1 interrupt. After protecting the breakpoint and the scene, it sends the IDLE instruction. The DSP pin level becomes low and responds to the external DMA request.
④ After 8237 takes over the bus, it first sends a DMA request response signal DACK to CS4235, indicating that CS4235 is allowed to perform DMA transfer. Then, according to the pre-set initial address and the number of bytes to be transferred, it sends the address and read and write commands in sequence, so that data can be directly exchanged between RAM CS4235 until all data are exchanged. [page]
⑤After the DMA transmission is completed, the bus request signal HRQ to the CPU is automatically canceled. At this time, the DSP detects the rising edge of the pin, and the DSP returns to the next instruction of the IDLE instruction. The DSP obtains control of the bus and continues to execute the program in INT1.
3 Software Interface between DSP and CS4235
The ISA bus interface of CS4235 is plug-and-play (PnP). The sound card must be activated by programming before the sound card registers can be directly accessed and configured to complete different tasks. In fact, the ISA slot designed for the old ISA card that is not PnP is also suitable for PnP cards. Only the corresponding changes need to be made in the software. The recognition process of DSP for PnP card is exactly the same as the recognition process of microcomputer for PnP card. Figure 6 shows the recognition program flow of DSP for PnP card. From the above PnP card recognition and configuration process, it can be seen that if it is in a PC environment, then this process can be completed automatically; in the system designed by the user, this process is somewhat cumbersome and not very meaningful. Can we bypass the PnP protocol and program each PnP card directly, just like the old ISA card? In fact, most chips do provide this simple and fast method, collectively referred to as the "certain company keyword" interface method. This article introduces this interface technology using CS4235 as an example. After completing the five steps given below, the sound card will operate the same as the old ISA sound card. The only drawback is that this method will not work if two sound cards of this type are used in the system.
① DSP sends 32 bytes of "Crystal Key" to address port 279H, and the PnP card immediately enters the configuration state. The 32 bytes of data are:
96, 35, 9A, CD, E6, F3, 79, BC, 5E, AF, 57, 2B, 15, 8A, C5, E2;
F1, F8, 7C, 3E, 9F, 4F, 27, 13, 09, 84, 42, A1, D0, 68, 34, 1A.
② DSP sends the handle number to 279H.
③ The DSP directly configures the configuration registers of each logic device to set the I/O port base address, interrupt number, and DMA channel selection.
④ DSP sends 79H to 279H to activate CS4235.
⑤ DSP prohibits the PnP card from participating in future PnP cycles.
After the above configuration is completed, CS4235 automatically exits the configuration state and enters normal operation, so that the registers of CS4235 can be directly programmed according to specific functional requirements.
Conclusion
In the fully digital language learning system, we use the sound effect chip CS4235 to replace the previously used voice recording and playback chip MSM6588. Although the hardware circuit design and software operation are much more complicated, the important indicators of the language learning system, such as passband, signal-to-noise ratio and distortion, have reached the sound quality standard of multimedia computers. Practice has shown that many key technologies and excellent design ideas in microcomputers can be transplanted into embedded systems, making embedded systems more colorful.
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